allow dimension shorthand for instance arrays

src/Language/SystemVerilog/Parser/ParseDecl.hs

@@ -182,6 +182,7 @@ parseDTsAsIntantiations (DTIdent _ name : tokens) =
                 follow = if null toks' then [] else step (tail toks')
                 asRange :: DeclToken -> Range
                 asRange (DTRange _ (NonIndexed, s)) = s
+                asRange (DTBit _ s) = (Number "0", BinOp Sub s (Number "1"))
                 asRange _ = failure
                 failure = error $ "unrecognized instantiation of " ++ name
                             ++ ": " ++ show inst
@@ -192,6 +193,7 @@ parseDTsAsIntantiations (DTIdent _ name : tokens) =
         isInstanceToken :: DeclToken -> Bool
         isInstanceToken (DTInstance{}) = True
         isInstanceToken (DTRange{}) = True
+        isInstanceToken (DTBit{}) = True
         isInstanceToken (DTIdent{}) = True
         isInstanceToken (DTComma{}) = True
         isInstanceToken _ = False

test/basic/instance_array.sv

@@ -4,11 +4,11 @@ module Example;
 endmodule
 
 module top;
-    Example e[2:0][4:5]();
-    defparam e[0][5].FOO = 1;
-    defparam e[0][4].FOO = 2;
+    Example e[3][4:5]();
+    defparam e[2][5].FOO = 1;
+    defparam e[2][4].FOO = 2;
     defparam e[1][5].FOO = 4;
     defparam e[1][4].FOO = 8;
-    defparam e[2][5].FOO = 16;
-    defparam e[2][4].FOO = 32;
+    defparam e[0][5].FOO = 16;
+    defparam e[0][4].FOO = 32;
 endmodule