Commit 5c0f414d by Zachary Snow

convert wildcard bindings before interfaces

parent 091520e4
...@@ -75,7 +75,6 @@ phases excludes = ...@@ -75,7 +75,6 @@ phases excludes =
, Convert.ParamType.convert , Convert.ParamType.convert
, Convert.SizeCast.convert , Convert.SizeCast.convert
, Convert.Simplify.convert , Convert.Simplify.convert
, Convert.StarPort.convert
, Convert.Stream.convert , Convert.Stream.convert
, Convert.Struct.convert , Convert.Struct.convert
, Convert.TFBlock.convert , Convert.TFBlock.convert
...@@ -94,6 +93,7 @@ phases excludes = ...@@ -94,6 +93,7 @@ phases excludes =
, Convert.Foreach.convert , Convert.Foreach.convert
, Convert.StringParam.convert , Convert.StringParam.convert
, selectExclude (Job.Interface, Convert.Interface.convert) , selectExclude (Job.Interface, Convert.Interface.convert)
, Convert.StarPort.convert
, selectExclude (Job.Always , Convert.AlwaysKW.convert) , selectExclude (Job.Always , Convert.AlwaysKW.convert)
, selectExclude (Job.Succinct , Convert.RemoveComments.convert) , selectExclude (Job.Succinct , Convert.RemoveComments.convert)
] ]
......
interface Interface(data);
input logic data;
initial #1 $display("Interface %b", data);
endinterface
module Module(intf);
Interface intf;
initial #2 $display("Module %b", intf.data);
endmodule
module top;
logic data;
Interface intf(.*);
Module m(.*);
initial begin
data = 0;
#1;
data = 1;
#1;
end
endmodule
module top;
reg data;
initial #1 $display("Interface %b", data);
initial #2 $display("Module %b", data);
initial begin
data = 0;
#1;
data = 1;
#1;
end
endmodule
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