Commit 59b416f9 by Zachary Snow

isolate interface name resolution checks

parent 6e8659a5
...@@ -37,6 +37,7 @@ ...@@ -37,6 +37,7 @@
* Fixed signed `struct` fields being converted to unsigned expressions when * Fixed signed `struct` fields being converted to unsigned expressions when
accessed directly accessed directly
* Fixed conversion of casts using structs containing multi-dimensional fields * Fixed conversion of casts using structs containing multi-dimensional fields
* Fixed incorrect name resolution conflicts raised during interface inlining
## v0.0.9 ## v0.0.9
......
`define TEST(loc, mod, expr) \
initial begin \
$display(`"loc mod.expr %b`", mod.expr); \
$display(`"loc loc.mod.expr %b`", loc.mod.expr); \
begin /* exciting shadowing */ \
localparam i = 1'bx; \
localparam j = 1'bz; \
$display(`"loc loc.mod.expr %b`", loc.mod.expr); \
end \
end
`define TEST_FUNC(loc, mod, expr) `TEST(loc, mod, expr())
`define TEST_TASK(loc, mod, expr) \
initial begin \
$display(`"loc mod.expr():`"); \
mod.expr(); \
$display(`"loc loc.mod.expr():`"); \
loc.mod.expr(); \
end
interface Intf;
parameter [3:0] P = 1;
localparam [3:0] L = 2;
wire [3:0] w;
assign w = 3;
modport D(input .x(w + 8'b1));
function automatic [3:0] F;
return -1;
endfunction
task T;
$display("T called");
endtask
if (1) begin : blk
parameter [3:0] P = 4;
localparam [3:0] L = 6;
reg [3:0] w;
initial w = 7;
function automatic [3:0] F;
return 8;
endfunction
task T;
$display("blk.T called");
endtask
end
endinterface
module ModAi(Intf i );
`TEST(ModAi, i, P)
`TEST(ModAi, i, L)
`TEST(ModAi, i, w)
`TEST_FUNC(ModAi, i, F)
`TEST_TASK(ModAi, i, T)
`TEST(ModAi, i, blk.P)
`TEST(ModAi, i, blk.L)
`TEST(ModAi, i, blk.w)
`TEST_FUNC(ModAi, i, blk.F)
`TEST_TASK(ModAi, i, blk.T)
endmodule
module ModAj(Intf j);
`TEST(ModAj, j, P)
`TEST(ModAj, j, L)
`TEST(ModAj, j, w)
`TEST_FUNC(ModAj, j, F)
`TEST_TASK(ModAj, j, T)
`TEST(ModAj, j, blk.P)
`TEST(ModAj, j, blk.L)
`TEST(ModAj, j, blk.w)
`TEST_FUNC(ModAj, j, blk.F)
`TEST_TASK(ModAj, j, blk.T)
endmodule
module ModBi(Intf.D i);
`TEST(ModBi, i, P)
`TEST(ModBi, i, L)
`TEST(ModBi, i, x)
endmodule
module ModBj(Intf.D j);
`TEST(ModBj, j, P)
`TEST(ModBj, j, L)
`TEST(ModBj, j, x)
endmodule
module top;
Intf i();
ModAi ai(i);
ModAj aj(i);
ModBi bi(i);
ModBj bj(i);
`TEST(top, i, P)
`TEST(top, i, L)
`TEST(top, i, w)
`TEST_FUNC(top, i, F)
`TEST_TASK(top, i, T)
`TEST(top, i, blk.P)
`TEST(top, i, blk.L)
`TEST(top, i, blk.w)
`TEST_FUNC(top, i, blk.F)
`TEST_TASK(top, i, blk.T)
endmodule
`define TEST(loc, mod, expr) \
initial begin \
$display(`"loc mod.expr %b`", i.expr); \
repeat (2) \
$display(`"loc loc.mod.expr %b`", top.i.expr); \
end
`define TEST_FUNC(loc, mod, expr) \
initial begin \
$display(`"loc mod.expr() %b`", i.expr(0)); \
repeat (2) \
$display(`"loc loc.mod.expr() %b`", top.i.expr(0)); \
end
`define TEST_TASK(loc, mod, expr) \
initial begin \
$display(`"loc mod.expr():`"); \
i.expr(); \
$display(`"loc loc.mod.expr():`"); \
top.i.expr(); \
end
module top;
if (1) begin : i
localparam [3:0] P = 1;
localparam [3:0] L = 2;
wire [3:0] w;
assign w = 3;
wire [7:0] x;
assign x = w + 8'b1;
function automatic [3:0] F;
input unused;
F = -1;
endfunction
task T;
$display("T called");
endtask
if (1) begin : blk
localparam [3:0] P = 4;
localparam [3:0] L = 6;
reg [3:0] w;
initial w = 7;
function automatic [3:0] F;
input unused;
F = 8;
endfunction
task T;
$display("blk.T called");
endtask
end
end
`TEST(ModAi, i, P)
`TEST(ModAi, i, L)
`TEST(ModAi, i, w)
`TEST_FUNC(ModAi, i, F)
`TEST_TASK(ModAi, i, T)
`TEST(ModAi, i, blk.P)
`TEST(ModAi, i, blk.L)
`TEST(ModAi, i, blk.w)
`TEST_FUNC(ModAi, i, blk.F)
`TEST_TASK(ModAi, i, blk.T)
`TEST(ModAj, j, P)
`TEST(ModAj, j, L)
`TEST(ModAj, j, w)
`TEST_FUNC(ModAj, j, F)
`TEST_TASK(ModAj, j, T)
`TEST(ModAj, j, blk.P)
`TEST(ModAj, j, blk.L)
`TEST(ModAj, j, blk.w)
`TEST_FUNC(ModAj, j, blk.F)
`TEST_TASK(ModAj, j, blk.T)
`TEST(ModBi, i, P)
`TEST(ModBi, i, L)
`TEST(ModBi, i, x)
`TEST(ModBj, j, P)
`TEST(ModBj, j, L)
`TEST(ModBj, j, x)
`TEST(top, i, P)
`TEST(top, i, L)
`TEST(top, i, w)
`TEST_FUNC(top, i, F)
`TEST_TASK(top, i, T)
`TEST(top, i, blk.P)
`TEST(top, i, blk.L)
`TEST(top, i, blk.w)
`TEST_FUNC(top, i, blk.F)
`TEST_TASK(top, i, blk.T)
endmodule
// pattern: inlining instance "mod" of module "Module" would make expression "a\[0\]\.x" used in "mod" resolvable when it wasn't previously
// location: interface_bad_expr_arr.sv:10:5
interface InterfaceA;
logic x;
endinterface
interface InterfaceB;
logic x;
endinterface
module Module(InterfaceB b);
assign a[0].x = 1;
endmodule
module top;
InterfaceA a[1]();
InterfaceB b();
Module mod(b);
endmodule
// pattern: inlining instance "mod" of module "Module" would make expression "x" used in "mod" resolvable when it wasn't previously
// location: interface_bad_expr_module.sv:6:5
interface Interface;
endinterface
module Module(Interface i);
assign x = 1;
endmodule
module top;
wire x;
Interface intf();
Module mod(intf);
endmodule
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