added (very hacky) PackedArrayFlatten conversion; convert logics in generate

Convert.hs

@@ -11,6 +11,7 @@ import Language.SystemVerilog.AST
 import qualified Convert.AlwaysKW
 import qualified Convert.Logic
 import qualified Convert.Typedef
+import qualified Convert.PackedArrayFlatten
 import qualified Convert.StarPort
 
 type Phase = AST -> AST
@@ -20,6 +21,7 @@ phases =
     [ Convert.AlwaysKW.convert
     , Convert.Logic.convert
     , Convert.Typedef.convert
+    , Convert.PackedArrayFlatten.convert
     , Convert.StarPort.convert
     ]
 

Convert/Logic.hs

@@ -13,6 +13,7 @@
 
 module Convert.Logic (convert) where
 
+import Data.Maybe (fromJust)
 import qualified Data.Set as Set
 
 import Language.SystemVerilog.AST
@@ -59,4 +60,22 @@ convertModuleItem idents (LocalNet (Logic mr) ident val) =
     LocalNet (t mr) ident val
     where
         t = if Set.member ident idents then Reg else Wire
+convertModuleItem idents (Generate items) = Generate $ map (convertGenItem $ convertModuleItem idents) items
 convertModuleItem _ other = other
+
+convertGenItem :: (ModuleItem -> ModuleItem) -> GenItem -> GenItem
+convertGenItem f item = convertGenItem' item
+    where
+        convertGenItem' :: GenItem -> GenItem
+        convertGenItem' (GenBlock x items) = GenBlock x $ map convertGenItem' items
+        convertGenItem' (GenFor a b c d items) = GenFor a b c d $ map convertGenItem' items
+        convertGenItem' (GenIf e i1 i2) = GenIf e (convertGenItem' i1) (convertGenItem' i2)
+        convertGenItem' (GenNull) = GenNull
+        convertGenItem' (GenModuleItem moduleItem) = GenModuleItem $ f moduleItem
+        convertGenItem' (GenCase e cases def) = GenCase e cases' def'
+            where
+                cases' = zip (map fst cases) (map (convertGenItem' . snd) cases)
+                def' = if def == Nothing
+                    then Nothing
+                    else Just $ convertGenItem' $ fromJust def
+

Language/SystemVerilog/AST.hs

@@ -21,6 +21,7 @@ module Language.SystemVerilog.AST
   , Case
   , Range
   , GenCase
+  , RangesOrAssignment
   ) where
 
 import Data.List
@@ -322,7 +323,7 @@ commas = intercalate ", "
 
 instance Show Stmt where
   show (Block                 Nothing       b  ) = printf "begin\n%s\nend" $ indent $ unlines' $ map show b
-  show (Block                 (Just (a, i)) b  ) = printf "begin : %s\n%s%s\nend" a $ indent $ unlines' $ (map show i ++ map show b)
+  show (Block                 (Just (a, i)) b  ) = printf "begin : %s\n%s\nend" a $ indent $ unlines' $ (map show i ++ map show b)
   show (Case                  a b Nothing      ) = printf "case (%s)\n%s\nendcase"                 (show a) (indent $ unlines' $ map showCase b)
   show (Case                  a b (Just c)     ) = printf "case (%s)\n%s\n\tdefault:\n%s\nendcase" (show a) (indent $ unlines' $ map showCase b) (indent $ indent $ show c)
   show (BlockingAssignment    a b              ) = printf "%s = %s;" (show a) (show b)
@@ -335,7 +336,7 @@ instance Show Stmt where
 
 data BlockItemDeclaration
   -- TODO: Maybe BIDReg should use [Range] for the first arg as well, but it's
-  -- really not clear to me what useful purpose this would have.
+  -- really not clear to me what *useful* purpose this would have.
   = BIDReg        (Maybe Range) Identifier [Range]
   | BIDParameter  Parameter
   | BIDLocalparam Localparam

sv2v.cabal

@@ -62,6 +62,7 @@ executable sv2v
     Convert
     Convert.AlwaysKW
     Convert.Logic
+    Convert.PackedArrayFlatten
     Convert.StarPort
     Convert.Typedef
     Convert.Template.ModuleItem