additional test coverage for existing logic

test/basic/assign_delay.sv

+module top;
+    reg x;
+    wire y;
+    assign #5 y = x;
+    initial begin
+        #1 x = 0;
+        #1 x = 1;
+        #20 x = 0;
+        #20 x = 1;
+    end
+endmodule

test/basic/attr.sv

@@ -10,7 +10,7 @@ endmodule
 (* a=1 *) module top;
     (* foo="bar" *) reg x;
     initial begin
-        x = 1;
+        (* bar = "baz" *) x = 1;
         $display(x);
     end
 

test/basic/gate.sv

@@ -12,11 +12,19 @@ module top;
     not (output_not, input_a);
     buf #2 foo_name (output_buf_delay, input_a);
 
+    wire output_nand, output_or, output_nor, output_xor, output_xnor;
+    nand (output_nand, input_a, input_b);
+    or (output_or, input_a, input_b);
+    nor (output_nor, input_a, input_b);
+    xor (output_xor, input_a, input_b);
+    xnor (output_xnor, input_a, input_b);
+
     initial repeat(2) begin
         $monitor("%3d ", $time,
             input_a, input_b,
             output_and, output_and_delay,
-            output_not, output_buf_delay);
+            output_not, output_buf_delay,
+            output_nand, output_or, output_nor, output_xor, output_xnor);
 
         #1;
         #1; input_a = 1;

test/core/assert.sv

@@ -5,8 +5,14 @@ module Module(input clock, input clear, input data);
     assert property (
         @(posedge clock) disable iff(clear) x == y
     );
+    named: assert property (
+        @(posedge clock) disable iff(clear) x == y
+    );
     task hello;
         $display("Hello!");
-        assert property (x == y);
     endtask
+    always @(posedge clock) begin
+        assert property (x == y);
+        named_stmt: assert property (x == y);
+    end
 endmodule

test/core/dimensions.sv

@@ -45,6 +45,8 @@ module top;
         $display("args %b", $size(RamPair, 1'h1));
         $display("args %b", $size(RamPair, 1'd1));
         $display("args %b", $size(RamPair, 1'dx));
+        $display("args %b", $size(RamPair, '0));
+        $display("args %b", $size(RamPair, 'x));
         $display("args %b", $size(RamPair, $bits(integer) - 31));
         $display("args %b", $size(integer, $bits(integer) - 31));
 

test/core/dimensions.v

@@ -42,6 +42,8 @@ module top;
         $display("args %b", 2);
         $display("args %b", 2);
         $display("args %b", 1'bx);
+        $display("args %b", 1'bx);
+        $display("args %b", 1'bx);
         $display("args %b", 2);
         $display("args %b", 32);
 

test/define/main.sv

+`START
+`ifdef DEFINED
+`ifndef NOT_DEFINED
+    initial $display("Hi");
+`endif
+`endif
+`END

test/define/main.v

+module top;
+    initial $display("Hi");
+endmodule

test/define/run.sh

+#!/bin/bash
+
+test_main() {
+    runAndCapture -DDEFINED -DEND=endmodule -D"START=module top;" main.sv
+    assertTrue "conversion should succeed" $result
+    assertNotNull "stdout should not be empty" "$stdout"
+    assertNull "stderr should be empty" "$stderr"
+
+    substituted=$SHUNIT_TMPDIR/main.sv
+    echo "$stdout" > $substituted
+    simpleTest $substituted main.v _
+}
+
+source ../lib/functions.sh
+
+. shunit2

test/nosim/do_while.sv

+module top;
+    initial do
+        $display("hi");
+    while (0);
+endmodule

test/nosim/drive_strength.sv

+module top;
+    wire (supply0, supply1) a = 1;
+    wire (strong1, strong0) b = 1;
+    wire (pull0, highz1) c = 1;
+    wire (pull1, highz0) d = 1;
+    wire (highz0, weak1) e = 1;
+    wire (highz1, weak0) f = 1;
+
+    wire u, v, w, x, y, z;
+    assign (supply0, supply1) u = 1;
+    assign (strong1, strong0) v = 1;
+    assign (pull0, highz1) w = 1;
+    assign (pull1, highz0) x = 1;
+    assign (highz0, weak1) y = 1;
+    assign (highz1, weak0) z = 1;
+endmodule

test/nosim/final.sv

+module top;
+    final $display("bye");
+endmodule

test/nosim/min_typ_max.sv

+module top;
+    initial #(1 : 2 : 3) $display("hi");
+endmodule

test/nosim/net_type.sv

+module top;
+`define TEST(kw) kw a_``kw;
+    `TEST(supply0)
+    `TEST(supply1)
+    `TEST(tri)
+    `TEST(triand)
+    `TEST(trior)
+    `TEST(trireg)
+    `TEST(tri0)
+    `TEST(tri1)
+    `TEST(uwire)
+    `TEST(wire)
+    `TEST(wand)
+    `TEST(wor)
+endmodule

test/nosim/non_integer_type.sv

+module top;
+    shortreal v [2];
+    real w [2];
+    realtime x [2];
+    string y [2];
+    event z [2];
+endmodule

test/nosim/real.sv

+module top;
+    real r = 3.14;
+    initial $display(r);
+endmodule

test/nosim/time.sv

+module top;
+    time t = 1s;
+    initial $display(t);
+endmodule

test/warning/localparam.sv

+localparam UNUSED = 1;

test/warning/run.sh

 #!/bin/bash
 
+NO_FILES_WARNING="Warning: No input files specified (try \`sv2v --help\`)"
 PACKAGE_WARNING="Warning: Source includes packages but no modules. Please convert packages alongside the modules that use them."
 INTERFACE_WARNING="Warning: Source includes an interface but output is empty because there is no top-level module which has no ports which are interfaces."
 
@@ -10,6 +11,13 @@ test_default() {
     assertNull "stderr should be empty" "$stderr"
 }
 
+test_no_files() {
+    runAndCapture
+    assertTrue "conversion should succeed" $result
+    assertNull "stdout should be empty" "$stdout"
+    assertEquals "stderr should should have warning" "$NO_FILES_WARNING" "$stderr"
+}
+
 test_only_package() {
     runAndCapture package.sv
     assertTrue "conversion should succeed" $result
@@ -38,6 +46,20 @@ test_only_interface_verbose() {
     assertEquals "stderr should have warning" "$INTERFACE_WARNING" "$stderr"
 }
 
+test_only_localparam() {
+    runAndCapture localparam.sv
+    assertTrue "conversion should succeed" $result
+    assertNull "stdout should be empty" "$stdout"
+    assertNull "stderr should be empty" "$stderr"
+}
+
+test_only_localparam_verbose() {
+    runAndCapture -v localparam.sv
+    assertTrue "conversion should succeed" $result
+    assertNotNull "stdout should not be empty" "$stdout"
+    assertNull "stderr should be empty" "$stderr"
+}
+
 source ../lib/functions.sh
 
 . shunit2