support module "list of param assignments" shorthand

src/Language/SystemVerilog/Parser/Parse.y

@@ -528,8 +528,14 @@ Params :: { [ModuleItem] }
   : {- empty -}          { [] }
   | "#" "(" ParamsFollow { map (MIPackageItem . Decl) $3 }
 ParamsFollow :: { [Decl] }
-  : ParameterDecl(")")              { $1 }
-  | ParameterDecl(",") ParamsFollow { $1 ++ $2 }
+  : ParamAsgn ")"              { [$1] }
+  | ParamAsgn "," ParamsFollow { $1 : $3 }
+  |               ParamsDecl   { $1 }
+ParamsDecl :: { [Decl] }
+  : ParameterDecl(")")            { $1 }
+  | ParameterDecl(",") ParamsDecl { $1 ++ $2 }
+ParamAsgn :: { Decl }
+  : Identifier "=" Expr { Param Parameter (Implicit Unspecified []) $1 $3 }
 
 PortDecls :: { ([Identifier], [ModuleItem]) }
   : "(" DeclTokens(")") { parseDTsAsPortDecls $2 }

test/basic/param_shorthand.sv

+module top #(FOO = 10);
+    initial $display(FOO);
+endmodule
+module top2 #(FOO = 10, BAR = 11);
+    initial $display(FOO, BAR);
+endmodule
+module top3 #(FOO = 10, BAR = 11, parameter BAZ = 12);
+    initial $display(FOO, BAR, BAZ);
+endmodule

test/basic/param_shorthand.v

+module top #(parameter FOO = 10);
+    initial $display(FOO);
+endmodule
+module top2 #(parameter FOO = 10, parameter BAR = 11);
+    initial $display(FOO, BAR);
+endmodule
+module top3 #(parameter FOO = 10, parameter BAR = 11, parameter BAZ = 12);
+    initial $display(FOO, BAR, BAZ);
+endmodule