Commit 4c49bd11 by Zachary Snow

function return type logic to implicit conversion

parent 9699f5bf
...@@ -13,6 +13,7 @@ import qualified Convert.AlwaysKW ...@@ -13,6 +13,7 @@ import qualified Convert.AlwaysKW
import qualified Convert.AsgnOp import qualified Convert.AsgnOp
import qualified Convert.CaseKW import qualified Convert.CaseKW
import qualified Convert.Enum import qualified Convert.Enum
import qualified Convert.FuncRet
import qualified Convert.Logic import qualified Convert.Logic
import qualified Convert.PackedArray import qualified Convert.PackedArray
import qualified Convert.Return import qualified Convert.Return
...@@ -27,6 +28,7 @@ type Phase = AST -> AST ...@@ -27,6 +28,7 @@ type Phase = AST -> AST
phases :: Target -> [Phase] phases :: Target -> [Phase]
phases YOSYS = phases YOSYS =
[ Convert.AsgnOp.convert [ Convert.AsgnOp.convert
, Convert.FuncRet.convert
, Convert.Enum.convert , Convert.Enum.convert
, Convert.PackedArray.convert , Convert.PackedArray.convert
, Convert.StarPort.convert , Convert.StarPort.convert
......
{- sv2v
- Author: Zachary Snow <zach@zachjs.com>
-
- Conversion which makes function `logic` return types implicit
-}
module Convert.FuncRet (convert) where
import Convert.Traverse
import Language.SystemVerilog.AST
convert :: AST -> AST
convert = traverseDescriptions $ traverseModuleItems convertFunction
convertFunction :: ModuleItem -> ModuleItem
convertFunction (Function ml (Logic r) f decls stmts) =
Function ml (Implicit r) f decls stmts
convertFunction other = other
...@@ -44,6 +44,7 @@ executable sv2v ...@@ -44,6 +44,7 @@ executable sv2v
Convert.AsgnOp Convert.AsgnOp
Convert.CaseKW Convert.CaseKW
Convert.Enum Convert.Enum
Convert.FuncRet
Convert.Logic Convert.Logic
Convert.PackedArray Convert.PackedArray
Convert.Return Convert.Return
......
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