fall back to lower-precedence multipack transformations

src/Convert/MultiplePacked.hs

@@ -229,7 +229,7 @@ convertExpr scopes =
         rewriteExpr (orig @ (Bit (Bit expr idxInner) idxOuter)) =
             if isJust maybeDims && expr == rewriteExpr expr
                 then Bit expr' idx'
-                else orig
+                else rewriteExprLowPrec orig
             where
                 maybeDims = dims expr
                 Just (dimInner, dimOuter, expr') = maybeDims
@@ -237,22 +237,10 @@ convertExpr scopes =
                 idxOuter' = orientIdx dimOuter idxOuter
                 base = BinOp Mul idxInner' (rangeSize dimOuter)
                 idx' = simplify $ BinOp Add base idxOuter'
-        rewriteExpr (orig @ (Bit expr idx)) =
-            if isJust maybeDims && expr == rewriteExpr expr
-                then Range expr' mode' range'
-                else orig
-            where
-                maybeDims = dims expr
-                Just (dimInner, dimOuter, expr') = maybeDims
-                mode' = IndexedPlus
-                idx' = orientIdx dimInner idx
-                len = rangeSize dimOuter
-                base = BinOp Add (endianCondExpr dimOuter (snd dimOuter) (fst dimOuter)) (BinOp Mul idx' len)
-                range' = (simplify base, simplify len)
         rewriteExpr (orig @ (Range (Bit expr idxInner) NonIndexed rangeOuter)) =
             if isJust maybeDims && expr == rewriteExpr expr
                 then rewriteExpr $ Range exprOuter IndexedMinus range
-                else orig
+                else rewriteExprLowPrec orig
             where
                 maybeDims = dims expr
                 exprOuter = Bit expr idxInner
@@ -264,7 +252,7 @@ convertExpr scopes =
         rewriteExpr (orig @ (Range (Bit expr idxInner) modeOuter rangeOuter)) =
             if isJust maybeDims && expr == rewriteExpr expr
                 then Range expr' modeOuter range'
-                else orig
+                else rewriteExprLowPrec orig
             where
                 maybeDims = dims expr
                 Just (dimInner, dimOuter, expr') = maybeDims
@@ -281,7 +269,23 @@ convertExpr scopes =
                 len = lenOuter
                 range' = (base, len)
                 one = RawNum 1
-        rewriteExpr (orig @ (Range expr NonIndexed range)) =
+        rewriteExpr other =
+            rewriteExprLowPrec other
+
+        rewriteExprLowPrec :: Expr -> Expr
+        rewriteExprLowPrec (orig @ (Bit expr idx)) =
+            if isJust maybeDims && expr == rewriteExpr expr
+                then Range expr' mode' range'
+                else orig
+            where
+                maybeDims = dims expr
+                Just (dimInner, dimOuter, expr') = maybeDims
+                mode' = IndexedPlus
+                idx' = orientIdx dimInner idx
+                len = rangeSize dimOuter
+                base = BinOp Add (endianCondExpr dimOuter (snd dimOuter) (fst dimOuter)) (BinOp Mul idx' len)
+                range' = (simplify base, simplify len)
+        rewriteExprLowPrec (orig @ (Range expr NonIndexed range)) =
             if isJust maybeDims && expr == rewriteExpr expr
                 then rewriteExpr $ Range expr IndexedMinus range'
                 else orig
@@ -292,7 +296,7 @@ convertExpr scopes =
                 base = endianCondExpr range baseDec baseInc
                 len = rangeSize range
                 range' = (base, len)
-        rewriteExpr (orig @ (Range expr mode range)) =
+        rewriteExprLowPrec (orig @ (Range expr mode range)) =
             if isJust maybeDims && expr == rewriteExpr expr
                 then Range expr' mode' range'
                 else orig
@@ -319,4 +323,4 @@ convertExpr scopes =
                 mode' = IndexedPlus
                 len = BinOp Mul sizeOuter lenOrig
                 range' = (base, len)
-        rewriteExpr other = other
+        rewriteExprLowPrec other = other

test/basic/multipack_prec.sv

+module top;
+    `include "multipack_prec.vh"
+
+    assign arr2[0][0] = arr1[0][0];
+    assign arr2[0][1] = arr1[0][1];
+    assign arr2[0][3:2] = arr1[0][3:2];
+    assign arr2[1][0+:2] = arr1[1][0+:2];
+    assign arr2[1][3-:2] = arr1[1][3-:2];
+endmodule

test/basic/multipack_prec.v

+module top;
+    `include "multipack_prec.vh"
+
+    assign arr2[0][0] = arr1[0][0];
+    assign arr2[0][1] = arr1[0][1];
+    assign arr2[0][3:2] = arr1[0][3:2];
+    // ideally we'd use the original as the reference, but the slices in the
+    // original fail due to steveicarus/iverilog#97
+    assign arr2[1][1:0] = arr1[1][1:0];
+    assign arr2[1][3:2] = arr1[1][3:2];
+endmodule

test/basic/multipack_prec.vh

+wire [3:0][2:0] arr1 [0:1];
+wire [0:1][3:0][2:0] arr2;
+
+assign arr1[0][0] = 3'b001;
+assign arr1[0][1] = 3'b011;
+assign arr1[0][2] = 3'b100;
+assign arr1[0][3] = 3'b010;
+assign arr1[1][0] = 3'b110;
+assign arr1[1][1] = 3'b100;
+assign arr1[1][2] = 3'b010;
+assign arr1[1][3] = 3'b101;