Commit 43883efa by Zachary Snow

fix partial packing of multidimensional unpacked arrays

parent 5fd21ebf
......@@ -60,9 +60,9 @@ rewriteDeclM (decl @ (Variable d t x a e)) = do
case usedAsPacked of
Just depth -> do
let (tf, rs) = typeRanges t
let (shifted, rest) = splitAt (length a - depth) a
let t' = tf $ shifted ++ rs
return $ Variable d t' x rest e
let (unpacked, packed) = splitAt depth a
let t' = tf $ packed ++ rs
return $ Variable d t' x unpacked e
Nothing -> return decl
rewriteDeclM decl @ Net{} = traverseNetAsVarM rewriteDeclM decl
rewriteDeclM other = return other
......
module example(
input wire [7:0] inp,
output wire [7:0] out
input wire inp [7:0],
output wire out [7:0]
);
assign out = ~inp;
for (genvar i = 0; i < 8; ++i)
assign out[i] = ~inp[i];
endmodule
module top;
reg arr1 [7:0][1:0];
reg arr2 [7:0][1:0][1:0];
wire [7:0] out1, out2;
reg arr1 [1:0][7:0];
reg arr2 [1:0][1:0][7:0];
wire out1 [7:0];
wire out2 [7:0];
example e1(arr1[0], out1);
example e2(arr2[0][0], out2);
initial begin
#1 arr1[0] = 8'hAD;
#1 arr2[0][0] = 8'h42;
for (integer i = 0; i < 8; ++i) begin
#1 arr1[0][i] = (8'hAD >> i) & 1'b1;
#1 arr2[0][0][i] = (8'h42 >> i) & 1'b1;
end
end
endmodule
......@@ -11,8 +11,11 @@ module top;
wire [7:0] out1, out2;
example e1(arr1[0], out1);
example e2(arr2[0][0], out2);
initial begin
#1 arr1[0] = 8'hAD;
#1 arr2[0][0] = 8'h42;
initial begin : blk
integer i;
for (i = 0; i < 8; i = i + 1) begin
#1 arr1[0][i] = (8'hAD >> i) & 1'b1;
#1 arr2[0][0][i] = (8'h42 >> i) & 1'b1;
end
end
endmodule
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