logic conversion ignores LHSs in procedural assignment senses

CHANGELOG.md

@@ -17,6 +17,8 @@
 
 * Fixed inadvertent design behavior changes caused by constant folding removing
   intentional width-extending operations such as `+ 0` and `* 1`
+* Fixed forced conversion to `reg` of data sensed in an edge-controlled
+  procedural assignment
 
 ## v0.0.9
 

src/Convert/Logic.hs

@@ -186,6 +186,9 @@ traverseStmtM :: Stmt -> ST Stmt
 traverseStmtM stmt@Timing{} =
     -- ignore the timing LHSs
     return stmt
+traverseStmtM (Asgn op Just{} lhs expr) =
+    -- ignore the timing LHSs
+    traverseStmtM $ Asgn op Nothing lhs expr
 traverseStmtM stmt@(Subroutine (Ident f) (Args (_ : Ident x : _) [])) =
     when (f == "$readmemh" || f == "$readmemb") (collectLHSM $ LHSIdent x)
         >> return stmt

test/core/asgn_sense_lhs.sv

+module mod(input clk);
+    logic x, y, z;
+    initial begin
+        $display(x, y, z);
+        z = 1;
+        x = @(posedge y or posedge clk) z;
+        $display(x, y, z);
+    end
+endmodule

test/core/asgn_sense_lhs.v

+module mod(input clk);
+    reg x, z;
+    wire y;
+    initial begin
+        $display(x, y, z);
+        z = 1;
+        x = @(posedge y or posedge clk) z;
+        $display(x, y, z);
+    end
+endmodule

test/core/asgn_sense_lhs_tb.v

+module top;
+    reg clk;
+    mod m(clk);
+    initial begin
+        $dumpvars(0, m);
+        clk = 0;
+        repeat (10)
+            #5 clk = ~clk;
+    end
+endmodule