conversion for splitting up port declaration variables

Convert.hs

@@ -13,6 +13,7 @@ import qualified Convert.CaseKW
 import qualified Convert.Logic
 import qualified Convert.Typedef
 import qualified Convert.PackedArrayFlatten
+import qualified Convert.SplitPortDecl
 import qualified Convert.StarPort
 
 type Phase = AST -> AST
@@ -24,6 +25,7 @@ phases =
     , Convert.Logic.convert
     , Convert.Typedef.convert
     , Convert.PackedArrayFlatten.convert
+    , Convert.SplitPortDecl.convert
     , Convert.StarPort.convert
     ]
 

Convert/PackedArrayFlatten.hs

@@ -115,15 +115,6 @@ unflattener outputs (arr, (t, (majorHi, majorLo))) =
                         (BinOp Sub size (Number "1")))
                     , Ident startBit )
 
-typeDims :: Type -> ([Range] -> Type, [Range])
-typeDims (Reg      r) = (Reg     , r)
-typeDims (Wire     r) = (Wire    , r)
-typeDims (Logic    r) = (Logic   , r)
-typeDims (Alias  t r) = (Alias  t, r)
-typeDims (Implicit r) = (Implicit, r)
-typeDims (IntegerT  ) = (error "ranges cannot be applied to IntegerT", [])
-typeDims (Enum t v r) = (Enum t v, r)
-
 prefix :: Identifier -> Identifier
 prefix ident = "_sv2v_" ++ ident
 

Convert/SplitPortDecl.hs

+{- sv2v
+ - Author: Zachary Snow <zach@zachjs.com>
+ -
+ - Conversion for splitting up complex port declarations. VTR doesn't support:
+ - `input wire foo;` but does suport: `input foo; wire foo;`.
+ -}
+
+module Convert.SplitPortDecl (convert) where
+
+import Convert.Traverse
+import Language.SystemVerilog.AST
+
+convert :: AST -> AST
+convert = traverseDescriptions convertDescription
+
+convertDescription :: Description -> Description
+convertDescription (Module name ports items) =
+    Module name ports (concat $ map splitPortDecl items)
+convertDescription other = other
+
+splitPortDecl :: ModuleItem -> [ModuleItem]
+splitPortDecl (orig @ (MIDecl (Variable Local _ _ _ _))) = [orig]
+splitPortDecl (orig @ (MIDecl (Variable _ (Implicit _) _ _ _))) = [orig]
+splitPortDecl (MIDecl (Variable d t x a me)) =
+    [ MIDecl $ Variable d     (Implicit r) x a Nothing
+    , MIDecl $ Variable Local t            x a me      ]
+    where (_, r) = typeDims t
+splitPortDecl other = [other]

Language/SystemVerilog/AST.hs

@@ -19,6 +19,7 @@ module Language.SystemVerilog.AST
   , Case
   , Range
   , GenCase
+  , typeDims
   ) where
 
 import Data.List
@@ -93,6 +94,15 @@ instance Show Type where
       showVal :: (Identifier, Maybe Expr) -> String
       showVal (x, e) = x ++ (showAssignment e)
 
+typeDims :: Type -> ([Range] -> Type, [Range])
+typeDims (Reg      r) = (Reg     , r)
+typeDims (Wire     r) = (Wire    , r)
+typeDims (Logic    r) = (Logic   , r)
+typeDims (Alias  t r) = (Alias  t, r)
+typeDims (Implicit r) = (Implicit, r)
+typeDims (IntegerT  ) = (error "ranges cannot be applied to IntegerT", [])
+typeDims (Enum t v r) = (Enum t v, r)
+
 data Decl
   = Parameter            Type Identifier Expr
   | Localparam           Type Identifier Expr

sv2v.cabal

@@ -65,6 +65,7 @@ executable sv2v
     Convert.CaseKW
     Convert.Logic
     Convert.PackedArrayFlatten
+    Convert.SplitPortDecl
     Convert.StarPort
     Convert.Typedef
     Convert.Traverse