Commit 2ee837f7 by Zachary Snow

restore port-decl hoisting for cleaner output

parent dca3a55f
......@@ -26,6 +26,7 @@ import qualified Convert.Struct
import qualified Convert.Typedef
import qualified Convert.UnbasedUnsized
import qualified Convert.Unique
import qualified Convert.HoistPortDecls
type Phase = AST -> AST
......@@ -37,6 +38,7 @@ phases excludes =
, selectExclude (Job.Logic , Convert.Logic.convert)
, Convert.FuncRet.convert
, Convert.Enum.convert
, Convert.HoistPortDecls.convert
, Convert.KWArgs.convert
, Convert.PackedArray.convert
, Convert.StarPort.convert
......
{- sv2v
- Author: Zachary Snow <zach@zachjs.com>
-
- VCS doesn't like port declarations inside of `generate` blocks, so we hoist
- them out with this conversion. This obviously isn't ideal, but it's
- relatively straightforward, and testing in VCS is important.
-}
module Convert.HoistPortDecls (convert) where
import Data.List (partition)
import Convert.Traverse
import Language.SystemVerilog.AST
convert :: AST -> AST
convert = traverseDescriptions hoistPortDecls
hoistPortDecls :: Description -> Description
hoistPortDecls (Part extern kw lifetime name ports items) =
Part extern kw lifetime name ports (concat $ map explode items)
where
explode :: ModuleItem -> [ModuleItem]
explode (Generate genItems) =
if null rest
then portDecls
else portDecls ++ [Generate rest]
where
(wrappedPortDecls, rest) = partition isPortDecl genItems
portDecls = map (\(GenModuleItem item) -> item) wrappedPortDecls
isPortDecl :: GenItem -> Bool
isPortDecl (GenModuleItem (MIDecl (Variable dir _ _ _ _))) =
dir /= Local
isPortDecl _ = False
explode other = [other]
hoistPortDecls other = other
......@@ -58,6 +58,7 @@ executable sv2v
Convert.Bits
Convert.Enum
Convert.FuncRet
Convert.HoistPortDecls
Convert.Interface
Convert.KWArgs
Convert.Logic
......
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