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lvzhengyang
sv2v
Commits
2150e8a4
Commit
2150e8a4
authored
Mar 08, 2019
by
Zachary Snow
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support optional tags in more places
parent
f40c71dc
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3 changed files
with
11 additions
and
8 deletions
+11
-8
src/Convert/PackedArray.hs
+1
-1
src/Language/SystemVerilog/AST.hs
+2
-2
src/Language/SystemVerilog/Parser/Parse.y
+8
-5
No files found.
src/Convert/PackedArray.hs
View file @
2150e8a4
...
@@ -157,7 +157,7 @@ unflattener writeToFlatVariant arr (t, (majorHi, majorLo)) =
...
@@ -157,7 +157,7 @@ unflattener writeToFlatVariant arr (t, (majorHi, majorLo)) =
(
index
,
majorLo
)
(
index
,
majorLo
)
(
BinOp
Le
(
Ident
index
)
majorHi
)
(
BinOp
Le
(
Ident
index
)
majorHi
)
(
index
,
AsgnOp
Add
,
Number
"1"
)
(
index
,
AsgnOp
Add
,
Number
"1"
)
(
prefix
"unflatten"
)
(
Just
$
prefix
"unflatten"
)
[
localparam
startBit
[
localparam
startBit
(
simplify
$
BinOp
Add
majorLo
(
simplify
$
BinOp
Add
majorLo
(
BinOp
Mul
(
Ident
index
)
size
))
(
BinOp
Mul
(
Ident
index
)
size
))
...
...
src/Language/SystemVerilog/AST.hs
View file @
2150e8a4
...
@@ -515,7 +515,7 @@ type GenCase = ([Expr], GenItem)
...
@@ -515,7 +515,7 @@ type GenCase = ([Expr], GenItem)
data
GenItem
data
GenItem
=
GenBlock
(
Maybe
Identifier
)
[
GenItem
]
=
GenBlock
(
Maybe
Identifier
)
[
GenItem
]
|
GenCase
Expr
[
GenCase
]
(
Maybe
GenItem
)
|
GenCase
Expr
[
GenCase
]
(
Maybe
GenItem
)
|
GenFor
(
Identifier
,
Expr
)
Expr
(
Identifier
,
AsgnOp
,
Expr
)
Identifier
[
GenItem
]
|
GenFor
(
Identifier
,
Expr
)
Expr
(
Identifier
,
AsgnOp
,
Expr
)
(
Maybe
Identifier
)
[
GenItem
]
|
GenIf
Expr
GenItem
GenItem
|
GenIf
Expr
GenItem
GenItem
|
GenNull
|
GenNull
|
GenModuleItem
ModuleItem
|
GenModuleItem
ModuleItem
...
@@ -529,7 +529,7 @@ instance Show GenItem where
...
@@ -529,7 +529,7 @@ instance Show GenItem where
show
(
GenCase
e
c
(
Just
d
))
=
printf
"case (%s)
\n
%s
\n\t
default:
\n
%s
\n
endcase"
(
show
e
)
(
indent
$
unlines'
$
map
showCase
c
)
(
indent
$
indent
$
show
d
)
show
(
GenCase
e
c
(
Just
d
))
=
printf
"case (%s)
\n
%s
\n\t
default:
\n
%s
\n
endcase"
(
show
e
)
(
indent
$
unlines'
$
map
showCase
c
)
(
indent
$
indent
$
show
d
)
show
(
GenIf
e
a
GenNull
)
=
printf
"if (%s) %s"
(
show
e
)
(
show
a
)
show
(
GenIf
e
a
GenNull
)
=
printf
"if (%s) %s"
(
show
e
)
(
show
a
)
show
(
GenIf
e
a
b
)
=
printf
"if (%s) %s
\n
else %s"
(
show
e
)
(
show
a
)
(
show
b
)
show
(
GenIf
e
a
b
)
=
printf
"if (%s) %s
\n
else %s"
(
show
e
)
(
show
a
)
(
show
b
)
show
(
GenFor
(
x1
,
e1
)
c
(
x2
,
o2
,
e2
)
x
is
)
=
printf
"for (%s = %s; %s; %s %s %s) %s"
x1
(
show
e1
)
(
show
c
)
x2
(
show
o2
)
(
show
e2
)
(
show
$
GenBlock
(
Just
x
)
is
)
show
(
GenFor
(
x1
,
e1
)
c
(
x2
,
o2
,
e2
)
mx
is
)
=
printf
"for (%s = %s; %s; %s %s %s) %s"
x1
(
show
e1
)
(
show
c
)
x2
(
show
o2
)
(
show
e2
)
(
show
$
GenBlock
mx
is
)
show
GenNull
=
";"
show
GenNull
=
";"
show
(
GenModuleItem
item
)
=
show
item
show
(
GenModuleItem
item
)
=
show
item
...
...
src/Language/SystemVerilog/Parser/Parse.y
View file @
2150e8a4
...
@@ -411,8 +411,8 @@ Stmt :: { Stmt }
...
@@ -411,8 +411,8 @@ Stmt :: { Stmt }
| Identifier ";" { Subroutine $1 [] }
| Identifier ";" { Subroutine $1 [] }
StmtNonAsgn :: { Stmt }
StmtNonAsgn :: { Stmt }
: ";" { Null }
: ";" { Null }
| "begin" DeclsAndStmts "end" { Block Nothing (fst $2) (snd $2) }
| "begin" DeclsAndStmts "end"
opt(Tag)
{ Block Nothing (fst $2) (snd $2) }
| "begin" ":" Identifier DeclsAndStmts "end" { Block (Just $3) (fst $4) (snd $4) }
| "begin" ":" Identifier DeclsAndStmts "end"
opt(Tag)
{ Block (Just $3) (fst $4) (snd $4) }
| "if" "(" Expr ")" Stmt "else" Stmt { If $3 $5 $7 }
| "if" "(" Expr ")" Stmt "else" Stmt { If $3 $5 $7 }
| "if" "(" Expr ")" Stmt %prec NoElse { If $3 $5 Null }
| "if" "(" Expr ")" Stmt %prec NoElse { If $3 $5 Null }
| "for" "(" Identifier "=" Expr ";" Expr ";" Identifier "=" Expr ")" Stmt { For ($3, $5) $7 ($9, $11) $13 }
| "for" "(" Identifier "=" Expr ";" Expr ";" Identifier "=" Expr ")" Stmt { For ($3, $5) $7 ($9, $11) $13 }
...
@@ -564,13 +564,16 @@ GenItems :: { [GenItem] }
...
@@ -564,13 +564,16 @@ GenItems :: { [GenItem] }
GenItem :: { GenItem }
GenItem :: { GenItem }
: "if" "(" Expr ")" GenItemOrNull "else" GenItemOrNull { GenIf $3 $5 $7 }
: "if" "(" Expr ")" GenItemOrNull "else" GenItemOrNull { GenIf $3 $5 $7 }
| "if" "(" Expr ")" GenItemOrNull %prec NoElse { GenIf $3 $5 GenNull }
| "if" "(" Expr ")" GenItemOrNull %prec NoElse { GenIf $3 $5 GenNull }
| "begin" GenItems "end" { GenBlock Nothing $2 }
| GenBlock { uncurry GenBlock $1 }
| "begin" ":" Identifier GenItems "end" { GenBlock (Just $3) $4 }
| "case" "(" Expr ")" GenCases opt(GenCaseDefault) "endcase" { GenCase $3 $5 $6 }
| "case" "(" Expr ")" GenCases opt(GenCaseDefault) "endcase" { GenCase $3 $5 $6 }
| "for" "(" Identifier "=" Expr ";" Expr ";" GenvarIteration ")"
"begin" ":" Identifier GenItems "end" { GenFor ($3, $5) $7 $9 $13 $14
}
| "for" "(" Identifier "=" Expr ";" Expr ";" GenvarIteration ")"
GenBlock { (uncurry $ GenFor ($3, $5) $7 $9) $11
}
-- TODO: We should restrict it to the module items that are actually allowed.
-- TODO: We should restrict it to the module items that are actually allowed.
| ModuleItem { genItemsToGenItem $ map GenModuleItem $1 }
| ModuleItem { genItemsToGenItem $ map GenModuleItem $1 }
GenBlock :: { (Maybe Identifier, [GenItem]) }
: "begin" GenItems "end" opt(Tag) { (Nothing, $2) }
| "begin" ":" Identifier GenItems "end" opt(Tag) { (Just $3, $4) }
GenCases :: { [GenCase] }
GenCases :: { [GenCase] }
: {- empty -} { [] }
: {- empty -} { [] }
| GenCases GenCase { $1 ++ [$2] }
| GenCases GenCase { $1 ++ [$2] }
...
...
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