Commit 1f05aa45 by Zachary Snow

add generated number tests

parent 0c319365
......@@ -38,6 +38,7 @@ All of sv2v's dependencies are free and open-source.
* Test Dependencies
* [Icarus Verilog](http://iverilog.icarus.com) - for Verilog simulation
* [shUnit2](https://github.com/kward/shunit2) - test framework
* Python (any version) - for generating certain test cases
## Installation
......
import math
import sys
def gen_digits(digits, size):
if size <= 0:
raise Exception("size must be positive")
elif size == 1:
for digit in digits:
yield digit
else:
for base in gen_digits(digits, size - 1):
for digit in digits:
yield base + digit
def gen(max_length, code, base, digits):
for length in range(1, max_length + 1):
min_bits = math.floor(1 + (length - 1) * math.log(base, 2))
max_bits = math.ceil(length * math.log(base, 2))
for number in gen_digits(digits, length):
yield "'" + code + number
yield "'s" + code + number
number_bin = number.replace("x", "0").replace("z", "0")
min_value = max(1, int(number_bin, base)) + 1
curr_min_bits = max(min_bits, math.ceil(math.log(min_value, 2)))
for bits in range(int(curr_min_bits), int(max_bits + 1)):
size = str(bits)
yield size + "'" + code + number
yield size + "'s" + code + number
if __name__ == "__main__":
assert len(sys.argv) == 5
max_length = int(sys.argv[1])
code = sys.argv[2]
base = int(sys.argv[3])
digits = sys.argv[4]
print('`define T(n) $display(`"n => %b => %0d`", n, $bits(n));')
print("module top;")
print("initial begin")
for number in gen(max_length, code, base, digits):
print("`T({})".format(number))
print("end")
print("endmodule")
#!/bin/bash
python gen.py 4 b 2 01xz > binary.sv
python gen.py 2 o 8 01234567xz > octal.sv
python gen.py 2 d 10 0123456789 > decimal.sv
python gen.py 2 h 16 0123456789abcdefxz > hex.sv
source ../lib/runner.sh
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