parse and convert empty function arguments (resolves #17)

src/Convert.hs

@@ -13,6 +13,7 @@ import qualified Convert.AlwaysKW
 import qualified Convert.AsgnOp
 import qualified Convert.Assertion
 import qualified Convert.Bits
+import qualified Convert.EmptyArgs
 import qualified Convert.Enum
 import qualified Convert.FuncRet
 import qualified Convert.Interface
@@ -42,6 +43,7 @@ phases excludes =
     , Convert.Bits.convert
     , selectExclude (Job.Logic    , Convert.Logic.convert)
     , Convert.FuncRet.convert
+    , Convert.EmptyArgs.convert
     , Convert.Enum.convert
     , Convert.IntTypes.convert
     , Convert.KWArgs.convert

src/Convert/EmptyArgs.hs

+{- sv2v
+ - Author: Zachary Snow <zach@zachjs.com>
+ -
+ - Verilog-2005 requires that all functions have at least one input port.
+ - SystemVerilog allows functions to have no arguments. This conversion adds a
+ - dummy argument to such functions.
+ -}
+
+module Convert.EmptyArgs (convert) where
+
+import Control.Monad.Writer
+import qualified Data.Set as Set
+
+import Convert.Traverse
+import Language.SystemVerilog.AST
+
+type Idents = Set.Set Identifier
+
+convert :: [AST] -> [AST]
+convert = map $ traverseDescriptions convertDescription
+
+convertDescription :: Description -> Description
+convertDescription description =
+    traverseModuleItems
+        (traverseExprs $ traverseNestedExprs $ convertExpr functions)
+        description'
+    where
+        (description', functions) =
+            runWriter $ traverseModuleItemsM traverseFunctionsM description
+
+traverseFunctionsM :: ModuleItem -> Writer Idents ModuleItem
+traverseFunctionsM (MIPackageItem (Function ml t f decls stmts)) = do
+    let dummyDecl = Variable Input (Implicit Unspecified []) "_sv2v_unused" [] Nothing
+    decls' <- do
+        if any isInput decls
+            then return decls
+            else do
+                tell $ Set.singleton f
+                return $ dummyDecl : decls
+    return $ MIPackageItem $ Function ml t f decls' stmts
+    where
+        isInput :: Decl -> Bool
+        isInput (Variable Input _ _ _ _) = True
+        isInput _ = False
+traverseFunctionsM other = return other
+
+convertExpr :: Idents -> Expr -> Expr
+convertExpr functions (Call Nothing func (Args [] [])) =
+    Call Nothing func (Args args [])
+    where args = if Set.member func functions
+            then [Just $ Number "0"]
+            else []
+convertExpr _ other = other

src/Language/SystemVerilog/Parser/Parse.y

@@ -615,6 +615,7 @@ ModuleInstantiation :: { [PortBinding] }
 
 TFItems :: { [Decl] }
   : "(" DeclTokens(")") ";" { parseDTsAsDecls $2 }
+  | "("            ")"  ";" { [] }
   |                     ";" { [] }
 
 ParamType :: { Type }

sv2v.cabal

@@ -57,6 +57,7 @@ executable sv2v
     Convert.AsgnOp
     Convert.Assertion
     Convert.Bits
+    Convert.EmptyArgs
     Convert.Enum
     Convert.FuncRet
     Convert.Interface

test/basic/empty_args.sv

+module top;
+    function automatic logic [31:0] nop();
+        return 32'h00000013;
+    endfunction
+    initial $display(nop());
+endmodule

test/basic/empty_args.v

+module top;
+    function automatic [31:0] nop;
+        input foo;
+        nop = 32'h00000013;
+    endfunction
+    initial $display(nop(0));
+endmodule