preliminary support for defparam

src/Convert/Traverse.hs

@@ -293,6 +293,8 @@ traverseExprsM mapper = moduleItemMapper
         declMapper decl >>= return . MIDecl
     moduleItemMapper (Assign lhs expr) =
         exprMapper expr >>= return . Assign lhs
+    moduleItemMapper (Defparam lhs expr) =
+        exprMapper expr >>= return . Defparam lhs
     moduleItemMapper (AlwaysC kw stmt) =
         stmtMapper stmt >>= return . AlwaysC kw
     moduleItemMapper (Initial stmt) =
@@ -334,6 +336,9 @@ traverseLHSsM mapper item =
         traverseModuleItemLHSsM (Assign lhs expr) = do
             lhs' <- traverseNestedLHSsM mapper lhs
             return $ Assign lhs' expr
+        traverseModuleItemLHSsM (Defparam lhs expr) = do
+            lhs' <- traverseNestedLHSsM mapper lhs
+            return $ Defparam lhs' expr
         traverseModuleItemLHSsM other = return other
 
 traverseLHSs :: Mapper LHS -> Mapper ModuleItem
@@ -460,6 +465,9 @@ traverseAsgnsM mapper = moduleItemMapper
         miMapperA (Assign lhs expr) = do
             (lhs', expr') <- mapper (lhs, expr)
             return $ Assign lhs' expr'
+        miMapperA (Defparam lhs expr) = do
+            (lhs', expr') <- mapper (lhs, expr)
+            return $ Defparam lhs' expr'
         miMapperA other = return other
 
         miMapperB = traverseStmtsM stmtMapper

src/Language/SystemVerilog/AST.hs

@@ -179,6 +179,7 @@ data ModuleItem
   = MIDecl     Decl
   | AlwaysC    AlwaysKW Stmt
   | Assign     LHS Expr
+  | Defparam   LHS Expr
   | Instance   Identifier [PortBinding] Identifier [PortBinding]
   | Genvar     Identifier
   | Generate   [GenItem]
@@ -208,6 +209,7 @@ instance Show ModuleItem where
     MIDecl     nest  -> show nest
     AlwaysC    k b   -> printf "%s %s" (show k) (show b)
     Assign     a b   -> printf "assign %s = %s;" (show a) (show b)
+    Defparam   a b   -> printf "defparam %s = %s;" (show a) (show b)
     Instance   m params i ports
       | null params -> printf "%s %s%s;"     m                    i (showPorts ports)
       | otherwise   -> printf "%s #%s %s%s;" m (showPorts params) i (showPorts ports)

src/Language/SystemVerilog/Parser/Lex.x

@@ -85,6 +85,7 @@ tokens :-
   "casex"            { tok KW_casex        }
   "casez"            { tok KW_casez        }
   "default"          { tok KW_default      }
+  "defparam"         { tok KW_defparam     }
   "do"               { tok KW_do           }
   "else"             { tok KW_else         }
   "end"              { tok KW_end          }

src/Language/SystemVerilog/Parser/Parse.y

@@ -28,6 +28,7 @@ import Language.SystemVerilog.Parser.Tokens
 "casex"            { Token KW_casex        _ _ }
 "casez"            { Token KW_casez        _ _ }
 "default"          { Token KW_default      _ _ }
+"defparam"         { Token KW_defparam     _ _ }
 "do"               { Token KW_do           _ _ }
 "else"             { Token KW_else         _ _ }
 "end"              { Token KW_end          _ _ }
@@ -322,6 +323,7 @@ ModuleItem :: { [ModuleItem] }
   : DeclTokens(";")  { parseDTsAsModuleItems $1 }
   | "parameter"  ParamType DeclAsgns ";" { map MIDecl $ map (uncurry $ Parameter  $2) $3 }
   | "localparam" ParamType DeclAsgns ";" { map MIDecl $ map (uncurry $ Localparam $2) $3 }
+  | "defparam" DefparamAsgns ";"         { map (uncurry Defparam) $2 }
   | "assign" LHS "=" Expr ";"            { [Assign $2 $4] }
   | AlwaysKW Stmt                        { [AlwaysC $1 $2] }
   | "initial" Stmt                       { [Initial $2] }
@@ -330,6 +332,12 @@ ModuleItem :: { [ModuleItem] }
   | "modport" ModportItems ";"           { map (uncurry Modport) $2 }
   | PackageItem                          { [MIPackageItem $1] }
 
+DefparamAsgns :: { [(LHS, Expr)] }
+  : DefparamAsgn                   { [$1] }
+  | DefparamAsgns "," DefparamAsgn { $1 ++ [$3] }
+DefparamAsgn :: { (LHS, Expr) }
+  : LHS "=" Expr { ($1, $3) }
+
 PackageItem :: { PackageItem }
   : "typedef" Type Identifier ";" { Typedef $2 $3 }
   | "function" opt(Lifetime) FuncRetAndName TFItems DeclsAndStmts "endfunction" opt(Tag) { Function $2 (fst $3) (snd $3) (map defaultFuncInput $ (map makeInput $4) ++ fst $5) (snd $5) }