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lvzhengyang
sv2v
Commits
1d216a2e
Commit
1d216a2e
authored
Aug 28, 2019
by
Zachary Snow
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preliminary ternary substitution simplification
parent
96034eb9
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4 changed files
with
69 additions
and
0 deletions
+69
-0
src/Convert.hs
+2
-0
src/Convert/Mux.hs
+65
-0
src/Language/SystemVerilog/AST/Expr.hs
+1
-0
sv2v.cabal
+1
-0
No files found.
src/Convert.hs
View file @
1d216a2e
...
...
@@ -20,6 +20,7 @@ import qualified Convert.Interface
import
qualified
Convert.IntTypes
import
qualified
Convert.KWArgs
import
qualified
Convert.Logic
import
qualified
Convert.Mux
import
qualified
Convert.NamedBlock
import
qualified
Convert.NestPI
import
qualified
Convert.Package
...
...
@@ -47,6 +48,7 @@ phases excludes =
,
Convert
.
Enum
.
convert
,
Convert
.
IntTypes
.
convert
,
Convert
.
KWArgs
.
convert
,
Convert
.
Mux
.
convert
,
Convert
.
PackedArray
.
convert
,
Convert
.
StarPort
.
convert
,
Convert
.
StmtBlock
.
convert
...
...
src/Convert/Mux.hs
0 → 100644
View file @
1d216a2e
{- sv2v
- Author: Zachary Snow <zach@zachjs.com>
-
- Elaboration of ternary expressions where the condition references a
- localparam.
-
- Our conversions generate a lot of ternary expressions. This conversion
- attempts to make the code output a bit cleaner. Note that we can only do this
- simplification on localparams because parameters can be overridden at
- instantiation.
-
- This conversion applies the heuristic that it will only make substitutions
- into a ternary condition if making substitutions immediately enables the
- expression to be simplified further.
-}
module
Convert.Mux
(
convert
)
where
import
Control.Monad.State
import
qualified
Data.Map.Strict
as
Map
import
Convert.Traverse
import
Language.SystemVerilog.AST
type
Info
=
Map
.
Map
Identifier
Expr
convert
::
[
AST
]
->
[
AST
]
convert
=
map
$
traverseDescriptions
convertDescription
convertDescription
::
Description
->
Description
convertDescription
=
scopedConversion
traverseDeclM
traverseModuleItemM
traverseStmtM
Map
.
empty
traverseDeclM
::
Decl
->
State
Info
Decl
traverseDeclM
decl
=
do
case
decl
of
Localparam
_
x
e
->
modify
$
Map
.
insert
x
e
_
->
return
()
return
decl
traverseModuleItemM
::
ModuleItem
->
State
Info
ModuleItem
traverseModuleItemM
item
=
traverseExprsM
traverseExprM
item
traverseStmtM
::
Stmt
->
State
Info
Stmt
traverseStmtM
stmt
=
traverseStmtExprsM
traverseExprM
stmt
traverseExprM
::
Expr
->
State
Info
Expr
traverseExprM
=
traverseNestedExprsM
$
stately
convertExpr
convertExpr
::
Info
->
Expr
->
Expr
convertExpr
info
(
Mux
cc
aa
bb
)
=
if
before
==
after
then
Mux
cc
aa
bb
else
simplify
$
Mux
after
aa
bb
where
before
=
traverseNestedExprs
substitute
(
simplify
cc
)
after
=
simplify
before
substitute
::
Expr
->
Expr
substitute
(
Ident
x
)
=
case
Map
.
lookup
x
info
of
Nothing
->
Ident
x
Just
e
->
e
substitute
other
=
other
convertExpr
_
other
=
other
src/Language/SystemVerilog/AST/Expr.hs
View file @
1d216a2e
...
...
@@ -125,6 +125,7 @@ simplify (orig @ (Call Nothing "$clog2" (Args [Just (Number n)] []))) =
case
readNumber
n
of
Nothing
->
orig
Just
x
->
Number
$
show
$
clog2
x
simplify
(
Mux
(
Number
"0"
)
e
_
)
=
e
simplify
(
Mux
(
BinOp
Ge
c1
c2
)
e1
e2
)
=
case
(
c1'
,
c2'
)
of
(
Number
a
,
Number
b
)
->
...
...
sv2v.cabal
View file @
1d216a2e
...
...
@@ -64,6 +64,7 @@ executable sv2v
Convert.IntTypes
Convert.KWArgs
Convert.Logic
Convert.Mux
Convert.NamedBlock
Convert.NestPI
Convert.Package
...
...
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