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lvzhengyang
sv2v
Commits
1a6e0ce9
Commit
1a6e0ce9
authored
Sep 04, 2019
by
Zachary Snow
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added support for inside expressions (closes #28)
parent
33bea9e6
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3 changed files
with
22 additions
and
1 deletions
+22
-1
src/Language/SystemVerilog/Parser/Parse.y
+2
-1
test/basic/inside_expr.sv
+9
-0
test/basic/inside_expr.v
+11
-0
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src/Language/SystemVerilog/Parser/Parse.y
View file @
1a6e0ce9
...
...
@@ -388,7 +388,7 @@ string { Token Lit_string _ _ }
%left "^" "^~" "~^"
%left "&" "~&"
%left "==" "!=" "===" "!==" "==?" "!=?"
%left "<" "<=" ">" ">="
%left "<" "<=" ">" ">="
"inside" "dist"
%left "<<" ">>" "<<<" ">>>"
%left "+" "-"
%left "*" "/" "%"
...
...
@@ -999,6 +999,7 @@ Expr :: { Expr }
| "'" "{" PatternItems "}" { Pattern $3 }
| "{" StreamOp StreamSize Concat "}" { Stream $2 $3 $4 }
| "{" StreamOp Concat "}" { Stream $2 (Number "1") $3 }
| Expr "inside" Concat { foldl1 (BinOp LogOr) $ map (BinOp Eq $1) $3 }
-- binary expressions
| Expr "||" Expr { BinOp LogOr $1 $3 }
| Expr "&&" Expr { BinOp LogAnd $1 $3 }
...
...
test/basic/inside_expr.sv
0 → 100644
View file @
1a6e0ce9
module
top
;
initial
for
(
logic
[
1
:
0
]
a
=
0
;
a
<
3
;
a
++
)
begin
if
(
a
inside
{
2'b01
,
2'b00
}
)
$
display
(
"fizz"
)
;
if
(
a
inside
{
2'b10
}
)
$
display
(
"buzz"
)
;
end
endmodule
test/basic/inside_expr.v
0 → 100644
View file @
1a6e0ce9
module
top
;
initial
begin
:
foo
reg
[
1
:
0
]
a
;
for
(
a
=
0
;
a
<
3
;
a
++
)
begin
if
(
a
==
2'b01
||
a
==
2'b00
)
$
display
(
"fizz"
)
;
if
(
a
==
2'b10
)
$
display
(
"buzz"
)
;
end
end
endmodule
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