allow empty parameter_port_list (resolves #83)

1687b1c5 · Zachary Snow · e7381c4d · 1687b1c5
Commit 1687b1c5 authored Mar 25, 2020 by Zachary Snow
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src/Language/SystemVerilog/Parser/Parse.y
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--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -559,6 +559,7 @@ PackageImportDeclaration :: { [ModuleItem] }
 Params :: { [ModuleItem] }
  : {- empty -}          { [] }
+  | "#" "(" ")"          { [] }
  | "#" "(" ParamsFollow { map (MIPackageItem . Decl) $3 }
 ParamsFollow :: { [Decl] }
  : ParamAsgn ")"              { [$1] }