simplify non-ANSI style port declaration dimensions

CHANGELOG.md

@@ -8,6 +8,8 @@
 ### Bug Fixes
 
 * Fixed an issue that prevented parsing tasks and functions with `inout` ports
+* Fixed certain non-ANSI style port declarations being incorrectly reported as
+  incompatible
 
 ## v0.0.11
 

src/Convert/ExprUtils.hs

@@ -14,6 +14,8 @@ module Convert.ExprUtils
     , endianCondRange
     , dimensionsSize
     , stringToNumber
+    , simplifyRange
+    , simplifyDimensions
     ) where
 
 import Data.Bits ((.&.), (.|.), shiftL, shiftR)
@@ -319,3 +321,9 @@ pattern ConvertedUU :: Integer -> Integer -> Integer -> Expr
 pattern ConvertedUU sz v k <- Repeat
     (RawNum sz)
     [Number (Based 1 True Binary v k)]
+
+simplifyRange :: Range -> Range
+simplifyRange (e1, e2) = (simplify e1, simplify e2)
+
+simplifyDimensions :: [Range] -> [Range]
+simplifyDimensions = map simplifyRange

src/Convert/PortDecl.hs

@@ -18,6 +18,7 @@ module Convert.PortDecl (convert) where
 import Data.List (intercalate, (\\))
 import Data.Maybe (mapMaybe)
 
+import Convert.ExprUtils (simplifyDimensions)
 import Convert.Traverse
 import Language.SystemVerilog.AST
 
@@ -102,9 +103,9 @@ combineDecls :: Decl -> Decl -> Decl
 combineDecls portDecl dataDecl
     | eP /= Nil =
         mismatch "invalid initialization at port declaration"
-    | aP /= aD =
+    | simplifyDimensions aP /= simplifyDimensions aD =
         mismatch "different unpacked dimensions"
-    | rsP /= rsD =
+    | simplifyDimensions rsP /= simplifyDimensions rsD =
         mismatch "different packed dimensions"
     | otherwise =
         base (tf rsD) ident aD Nil

test/basic/port_decl_simplify.sv

+module top(out);
+    output [32 - 1:0] out;
+    reg [31:0] out;
+endmodule