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lvzhengyang
sv2v
f9917d94da51a09812cb1356ab2cd4971b86b88a
f9917d94da51a09812cb1356ab2cd4971b86b88a
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sv2v
test
core
output_implicit_tb.v
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output_implicit_tb.v
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default implicit output ports to logic
e0d425d9
Zachary Snow
committed
3 years ago
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module
top
;
wire
o1
,
o2
;
mod
m
(
o1
,
o2
)
;
endmodule