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lvzhengyang
sv2v
a80919b72a2d6bad7cc7077051c2fb7bcbc4b830
a80919b72a2d6bad7cc7077051c2fb7bcbc4b830
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sv2v
test
core
uniop_prec.sv
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uniop_prec.sv
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updated binary and unary operator printing (resolves #72)
b124a561
Zachary Snow
committed
5 years ago
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module
Example
(
a
,
b
)
;
input
logic
[
1
:
0
]
a
;
output
logic
b
;
assign
b
=
!
(
&
a
)
;
endmodule