{- sv2v - Author: Zachary Snow <zach@zachjs.com> - - Conversion for `signed` and `unsigned` type casts. - - SystemVerilog has `signed'(foo)` and `unsigned'(foo)` as syntactic sugar for - the `$signed` and `$unsigned` system functions present in Verilog-2005. This - conversion elaborates these casts. -}moduleConvert.SignCast(convert)whereimportConvert.TraverseimportLanguage.SystemVerilog.ASTconvert::[AST]->[AST]convert=map$traverseDescriptions$traverseModuleItems$traverseExprs$traverseNestedExprsconvertExprconvertExpr::Expr->ExprconvertExpr(Cast(Left(ImplicitSigned[]))e)=Call(Ident"$signed")(Args[Juste][])convertExpr(Cast(Left(ImplicitUnsigned[]))e)=Call(Ident"$unsigned")(Args[Juste][])convertExprother=other