This fixes a regression where we don't have an instruction for pre Armv8.2-a
to do a move of an fp16 value from a GP reg to a SIMD reg.
This patch adds that pattern to movhf_aarch64 using a dup and only selectes it
using a very low priority.
This fixes an ICE at -O0.
gcc/
2018-06-20 Tamar Christina <tamar.christina@arm.com>
PR target/85769
* config/aarch64/aarch64.md (*movhf_aarch64): Add dup v0.4h pattern.
gcc/testsuite/
2018-06-20 Tamar Christina <tamar.christina@arm.com>
PR target/85769
* gcc.target/aarch64/f16_mov_immediate_3.c: New.
From-SVN: r262178
