Some patterns are using '%w2' for immediate operands, which means that a zero
immediate is actually emitted as 'wzr' or 'xzr'. This not only changes an
immediate operand into a register operand but may emit illegal instructions
from legal RTL (eg. ORR x0, SP, xzr rather than ORR x0, SP, 0).
* config/aarch64/aarch64.md
(add<mode>3_compareC_cconly_imm): Remove use of %w.
(add<mode>3_compareC_imm): Likewise.
(<optab>si3_uxtw): Split into register and immediate variants.
(andsi3_compare0_uxtw): Likewise.
(and<mode>3_compare0): Likewise.
(and<mode>3nr_compare0): Likewise.
(stack_protect_test_<mode>): Don't use %x for memory operands.
From-SVN: r236285
