The pattern:
;; <su>q<addsub>
(define_insn "aarch64_<su_optab><optab><mode>"
[(set (match_operand:VSDQ_I 0 "register_operand" "=w")
(BINQOPS:VSDQ_I (match_operand:VSDQ_I 1 "register_operand" "w")
(match_operand:VSDQ_I 2 "register_operand" "w")))]
"TARGET_SIMD"
"<su_optab><optab>\\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
[(set_attr "type" "neon_<optab><q>")]
)
meant that we overloaded "optab" to be "qadd" for both SQADD and
UQADD. Most other "optab" entries are instead the full optab name,
which for these patterns would be "ssadd" and "usadd" respectively.
(Unfortunately, the optabs don't extend to vectors yet, something
that would be good to fix in GCC 11.)
This patch therefore does what the comment implies and uses
q<addsub> to distinguish qadd and qsub instead.
2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/iterators.md (addsub): New code attribute.
* config/aarch64/aarch64-simd.md (aarch64_<su_optab><optab><mode>):
Re-express as...
(aarch64_<su_optab>q<addsub><mode>): ...this, making the same change
in the asm string and attributes. Fix indentation.
* config/aarch64/aarch64-sve.md (@aarch64_<su_optab><optab><mode>):
Re-express as...
(@aarch64_sve_<optab><mode>): ...this.
* config/aarch64/aarch64-sve-builtins.h
(function_expander::expand_signed_unpred_op): Delete.
* config/aarch64/aarch64-sve-builtins.cc
(function_expander::expand_signed_unpred_op): Likewise.
(function_expander::map_to_rtx_codes): If the optab isn't defined,
try using code_for_aarch64_sve instead.
* config/aarch64/aarch64-sve-builtins-base.cc (svqadd_impl): Delete.
(svqsub_impl): Likewise.
(svqadd, svqsub): Use rtx_code_function instead.
From-SVN: r280050
