The RISC-V user ISA permits misaligned accesses, but they may trap
and be emulated.  That emulation software needs to be compiled assuming
strict alignment.

Even when strict alignment is not required, set SLOW_UNALIGNED_ACCESS
based upon -mtune to avoid a performance pitfall.

gcc/ChangeLog:

2017-05-04  Andrew Waterman  <andrew@sifive.com>

	* config/riscv/riscv.opt (mstrict-align): New option.
	* config/riscv/riscv.h (STRICT_ALIGNMENT): Use it.  Update comment.
	(SLOW_UNALIGNED_ACCESS): Define.
	(riscv_slow_unaligned_access): Declare.
	* config/riscv/riscv.c (riscv_tune_info): Add slow_unaligned_access
	field.
	(riscv_slow_unaligned_access): New variable.
	(rocket_tune_info): Set slow_unaligned_access to true.
	(optimize_size_tune_info): Set slow_unaligned_access to false.
	(riscv_cpu_info_table): Add entry for optimize_size_tune_info.
	(riscv_valid_lo_sum_p): Use TARGET_STRICT_ALIGN.
	(riscv_option_override): Set riscv_slow_unaligned_access.
        * doc/invoke.texi: Add -mstrict-align to RISC-V.

From-SVN: r247659