Use the STLUR instruction introduced in Armv8.4-a.
This instruction has the store-release semantic like STLR but can take a
9-bit unscaled signed immediate offset.

Example test case:
```
void
foo ()
{
    int32_t *atomic_vals = calloc (4, sizeof (int32_t));
    atomic_store_explicit (atomic_vals + 1, 2, memory_order_release);
}
```

Before patch generates
```
foo:
	stp	x29, x30, [sp, -16]!
	mov	x1, 4
	mov	x0, x1
	mov	x29, sp
	bl	calloc
	mov	w1, 2
	add	x0, x0, 4
	stlr	w1, [x0]
	ldp	x29, x30, [sp], 16
	ret
```

After patch generates
```
foo:
	stp	x29, x30, [sp, -16]!
	mov	x1, 4
	mov	x0, x1
	mov	x29, sp
	bl	calloc
	mov	w1, 2
	stlur	w1, [x0, 4]
	ldp	x29, x30, [sp], 16
	ret
```

We introduce a new feature flag to indicate the presence of this instruction.
The feature flag is called AARCH64_ISA_RCPC8_4 and is included when targeting
armv8.4 architecture.

We also introduce an "arch" attribute to be checked called "rcpc8_4" after this
feature flag.

gcc/

2018-09-19  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/aarch64/aarch64-protos.h
	(aarch64_offset_9bit_signed_unscaled_p): New declaration.
	* config/aarch64/aarch64.md (arches): New "rcpc8_4" attribute value.
	(arch_enabled): Add check for "rcpc8_4" attribute value of "arch".
	* config/aarch64/aarch64.h (AARCH64_FL_RCPC8_4): New bitfield.
	(AARCH64_FL_FOR_ARCH8_4): Include AARCH64_FL_RCPC8_4.
	(AARCH64_FL_PROFILE): Move index so flags are ordered.
	(AARCH64_ISA_RCPC8_4): New flag.
	* config/aarch64/aarch64.c (offset_9bit_signed_unscaled_p): Renamed
	to aarch64_offset_9bit_signed_unscaled_p.
	* config/aarch64/atomics.md (atomic_store<mode>): Allow offset
	and use stlur.
	* config/aarch64/constraints.md (Ust): New constraint.
	* config/aarch64/predicates.md.
	(aarch64_9bit_offset_memory_operand): New predicate.
	(aarch64_rcpc_memory_operand): New predicate.

gcc/testsuite/

2018-09-19  Matthew Malcomson  <matthew.malcomson@arm.com>

	* gcc.target/aarch64/atomic-store.c: New.

From-SVN: r264421