(extendqidi2, extendhidi2, extendsidi2): Allow "general_operand" instead
of "register_operand" 0.
(adddid_sexthishl32, subdid_sexthishl32, subdi_dishl32): Likewise.
(adddi_dilshr32): Operand 0 constraint changed from "ro" to "do";
Code generation fixed.
(adddi_mem, subdi_mem): Fixed for "<" and ">" operand 0.
(adddi3, subdi3): Operand 2 constraint changed from "ao" to "*ao"
(ashldi_sexthi, ashrdi_const32): Allow only "register_operand"
instead of "general_operand" 0.
(ash[lr]di_const, ash[lr]di3): Allow also 8 and 16 as shift count.
(subreg1ashrdi_const32): Pattern deleted.
(subreghi1ashrdi_const32, subregsi1ashrdi_const32): New pattern.
(lshrsi_31): New implementation.
(scc0_di, scc_di, beq0_di, bne0_di, bge0_di, blt0_di): New patterns.

From-SVN: r9666