On AArch64 aarch64_classify_address has a case for when it's non-strict
that will allow it to accept any byte offset from a reg when validating
an address in a given addressing mode.
This because reload would later make the address valid. SVE however requires
the address always be valid, but currently allows any address when a MEM +
offset is used. This causes an ICE as nothing later forces the address to be
legitimate.
The patch forces aarch64_emit_sve_pred_move via expand_insn to ensure that
the addressing mode is valid for any loads/stores it creates, which follows
the SVE way of handling address classifications.
gcc/ChangeLog:
PR target/88847
* config/aarch64/aarch64-sve.md (*pred_mov<mode>, pred_mov<mode>):
Expose as @aarch64_pred_mov.
* config/aarch64/aarch64.c (aarch64_classify_address):
Use expand_insn which legitimizes operands.
gcc/testsuite/ChangeLog:
PR target/88847
* gcc.target/aarch64/sve/pr88847.c: New test.
From-SVN: r268845
