- Implied rule are introduced into latest RISC-V ISA spec.

  - Only implemented D implied F-extension. Zicsr and Zifence are not
    implement yet, so the rule not included in this patch.

  - Pass preprocessed arch string to arch.

  - Verified with binutils 2.30 and 2.34.

gcc/ChangeLog

	* common/config/riscv/riscv-common.c (riscv_implied_info_t): New.
	(riscv_implied_info): New.
	(riscv_subset_list): Add handle_implied_ext.
	(riscv_subset_list::to_string): New parameter version_p to
	control output format.
	(riscv_subset_list::handle_implied_ext): New.
	(riscv_subset_list::parse_std_ext): Call handle_implied_ext.
	(riscv_arch_str): New parameter version_p to control output format.
	(riscv_expand_arch): New.
	* config/riscv/riscv-protos.h (riscv_arch_str): New parameter,
	version_p.
	* config/riscv/riscv.h (riscv_expand_arch): New,
	(EXTRA_SPEC_FUNCTIONS): Define.
	(ASM_SPEC): Transform -march= via riscv_expand_arch.

gcc/testsuite/ChangeLog

	* gcc.target/riscv/arch-6.c: New.
	* gcc.target/riscv/attribute-11.c: New.
	* gcc.target/riscv/attribute-12.c: New.

 - The arch string rule has changed in latest spec, it introduced new
   multi-letter extension prefix with 'h' and 'z', and drop `sx`. also
   adjust parsing order for 's' and 'x'.

gcc/ChangeLog

	* riscv-common.c (parse_sv_or_non_std_ext): Rename to
	parse_multiletter_ext.
	(parse_multiletter_ext): Add parsing `h` and `z`, drop `sx`,
	adjust parsing order for 's' and 'x'.

gcc/testsuite/ChangeLog

	* gcc.target/riscv/arch-3.c: Adjust option.
	* gcc.target/riscv/arch-5.c: New.
	* gcc.target/riscv/attribute-9.c: Adjust option and test
	condition.

	gcc/
	* config.gcc:  Add riscv-shorten-memrefs.o to extra_objs for riscv.
	* config/riscv/riscv-passes.def: New file.
	* config/riscv/riscv-protos.h (make_pass_shorten_memrefs): Declare.
	* config/riscv/riscv-shorten-memrefs.c: New file.
	* config/riscv/riscv.c (tree-pass.h): New include.
	(riscv_compressed_reg_p): New Function
	(riscv_compressed_lw_offset_p): Likewise.
	(riscv_compressed_lw_address_p): Likewise.
	(riscv_shorten_lw_offset): Likewise.
	(riscv_legitimize_address): Attempt to convert base + large_offset
	to compressible new_base + small_offset.
	(riscv_address_cost): Make anticipated compressed load/stores
	cheaper for code size than uncompressed load/stores.
	(riscv_register_priority): Move compressed register check to
	riscv_compressed_reg_p.
	* config/riscv/riscv.h (C_S_BITS): Define.
	(CSW_MAX_OFFSET): Define.
	* config/riscv/riscv.opt (mshorten-memefs): New option.
	* config/riscv/t-riscv (riscv-shorten-memrefs.o): New rule.
	(PASSES_EXTRA): Add riscv-passes.def.
	* doc/invoke.texi: Document -mshorten-memrefs.

	* config/riscv/riscv.c (riscv_new_address_profitable_p): New function.
	(TARGET_NEW_ADDRESS_PROFITABLE_P): Define.
	* doc/tm.texi: Regenerate.
	* doc/tm.texi.in (TARGET_NEW_ADDRESS_PROFITABLE_P):  New hook.
	* sched-deps.c (attempt_change): Use old address if it is cheaper than
	new address.
	* target.def (new_address_profitable_p): New hook.
	* targhooks.c (default_new_address_profitable_p): New function.
	* targhooks.h (default_new_address_profitable_p): Declare.

	gcc/testsuite/
	* gcc.target/riscv/shorten-memrefs-1.c: New test.
	* gcc.target/riscv/shorten-memrefs-2.c: New test.
	* gcc.target/riscv/shorten-memrefs-3.c: New test.
	* gcc.target/riscv/shorten-memrefs-4.c: New test.
	* gcc.target/riscv/shorten-memrefs-5.c: New test.
	* gcc.target/riscv/shorten-memrefs-6.c: New test.
	* gcc.target/riscv/shorten-memrefs-7.c: New test.

2020-07-21  Uroš Bizjak  <ubizjak@gmail.com>

gcc/ChangeLog:

	* config/i386/i386.h (TARGET_AVOID_MFENCE):
	Rename from TARGET_USE_XCHG_FOR_ATOMIC_STORE.
	* config/i386/sync.md (atomic_store<mode>): Update for rename.
	* config/i386/x86-tune.def (X86_TUNE_AVOID_MFENCE):
	Rename from X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE.

	* gcc.pot: Regenerate.

gcc/

	* Makefile.in (SELFTEST_DEPS): Move before including language makefile
	fragments.

(cherry picked from commit b19d8aac15649f31a7588b2634411a1922906ea8)

Squashed with commit f842bdd7a97e9fef7513a266d641cac72d5f97cc

gcc/ChangeLog:

	* config.in: Regenerate.
	* config/s390/s390.c (print_operand): Emit vector alignment hints
	for target z13, if AS accepts them.  For other targets the logic
	stays the same.
	* config/s390/s390.h (TARGET_VECTOR_LOADSTORE_ALIGNMENT_HINTS): Define
	macro.
	* configure: Regenerate.
	* configure.ac: Check HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS_ON_Z13.

gcc/testsuite/ChangeLog:

	* gcc.target/s390/vector/align-1.c: Change target architecture
	to z13.
	* gcc.target/s390/vector/align-2.c: Change target architecture
	to z13.

(cherry picked from commit 929fd91ba975eebf9e57f7f092041271dcaf0c34)

This is a release branch version of
r11-1741-g:31427b974ed7b7dd54e28fec595e731bf6eea8ba and
r11-2022-g:efe99cca78215e339ba79f0a900a896b4c0a3d36.

The trunk versions of the patch made GNU and Advanced SIMD vectors
distinct (but inter-convertible) in all cases.  However, the
traditional behaviour is that the types are distinct in template
arguments but not otherwise.

Following a suggestion from Jason, this patch puts the check
for different vector types under comparing_specializations.
In order to keep the backport as simple as possible, the patch
hard-codes the name of the attribute in the frontend rather than
adding a new branch-only target hook.

I didn't find a test that tripped the assert on the branch,
even with the --param in the PR, so instead I tested this by
forcing the hash function to only hash the tree code.  That made
the static assertion in the test fail without the patch but pass
with it.

This means that the tests pass for unmodified sources even
without the patch (unless you're very unlucky).

gcc/
	PR target/95726
	* config/aarch64/aarch64.c (aarch64_attribute_table): Add
	"Advanced SIMD type".
	* config/aarch64/aarch64-builtins.c: Include stringpool.h and
	attribs.h.
	(aarch64_init_simd_builtin_types): Add an "Advanced SIMD type"
	attribute to each Advanced SIMD type.
	* config/arm/arm.c (arm_attribute_table): Add "Advanced SIMD type".
	* config/arm/arm-builtins.c: Include stringpool.h and attribs.h.
	(arm_init_simd_builtin_types): Add an "Advanced SIMD type"
	attribute to each Advanced SIMD type.

gcc/cp/
	PR target/95726
	* typeck.c (structural_comptypes): When comparing template
	specializations, differentiate between vectors that have and
	do not have an "Advanced SIMD type" attribute.

gcc/testsuite/
	PR target/95726
	* g++.target/aarch64/pr95726.C: New test.
	* g++.target/arm/pr95726.C: Likewise.

The _mm512_{,mask_}cmp_p[ds]_mask and also _mm_{,mask_}cmp_s[ds]_mask
intrinsics have an argument which must have a constant passed to it
and so use an inline version only for ifdef __OPTIMIZE__ and have
a #define for -O0.  But the _mm512_{,mask_}cmp*_p[ds]_mask intrinsics
don't need a constant argument, they are essentially the first
set with the constant added to them implicitly based on the comparison
name, and so there is no #define version for them (correctly).
But their inline versions are defined in between the first and s[ds]
set and so inside of ifdef __OPTIMIZE__, which means that with -O0
they aren't defined at all.

This patch fixes that by moving those after the #ifdef __OPTIMIZE #else
use #define #endif block.

2020-07-15  Jakub Jelinek  <jakub@redhat.com>

	PR target/96174
	* config/i386/avx512fintrin.h (_mm512_cmpeq_pd_mask,
	_mm512_mask_cmpeq_pd_mask, _mm512_cmplt_pd_mask,
	_mm512_mask_cmplt_pd_mask, _mm512_cmple_pd_mask,
	_mm512_mask_cmple_pd_mask, _mm512_cmpunord_pd_mask,
	_mm512_mask_cmpunord_pd_mask, _mm512_cmpneq_pd_mask,
	_mm512_mask_cmpneq_pd_mask, _mm512_cmpnlt_pd_mask,
	_mm512_mask_cmpnlt_pd_mask, _mm512_cmpnle_pd_mask,
	_mm512_mask_cmpnle_pd_mask, _mm512_cmpord_pd_mask,
	_mm512_mask_cmpord_pd_mask, _mm512_cmpeq_ps_mask,
	_mm512_mask_cmpeq_ps_mask, _mm512_cmplt_ps_mask,
	_mm512_mask_cmplt_ps_mask, _mm512_cmple_ps_mask,
	_mm512_mask_cmple_ps_mask, _mm512_cmpunord_ps_mask,
	_mm512_mask_cmpunord_ps_mask, _mm512_cmpneq_ps_mask,
	_mm512_mask_cmpneq_ps_mask, _mm512_cmpnlt_ps_mask,
	_mm512_mask_cmpnlt_ps_mask, _mm512_cmpnle_ps_mask,
	_mm512_mask_cmpnle_ps_mask, _mm512_cmpord_ps_mask,
	_mm512_mask_cmpord_ps_mask): Move outside of __OPTIMIZE__ guarded
	section.

	* gcc.target/i386/avx512f-vcmppd-3.c: New test.
	* gcc.target/i386/avx512f-vcmpps-3.c: New test.

(cherry picked from commit 12d69dbfff9dd5ad4a30b20d1636f5cab6425e8c)

This reverts commit 8147c741.

2020-07-15  Richard Biener  <rguenther@suse.de>

	PR bootstrap/96203
	* lto-opts.c: Revert changes.
	* lto-wrapper.c: Likewise.

convert_like issues errors about bad_p conversions at the beginning
of the function, but in the ck_ref_bind case, it only issues them
after we've called convert_like on the next conversion.

This doesn't work as expected since r10-7096 because when we see
a conversion from/to class type in a template, we return early, thereby
missing the error, and a bad_p conversion goes by undetected.  That
made the attached test to compile even though it should not.

I had thought that I could just move the ck_ref_bind/bad_p errors
above to the rest of them, but that regressed diagnostics because
expr then wasn't converted yet by the nested convert_like_real call.

So, for bad_p conversions, do the normal processing, but still return
the IMPLICIT_CONV_EXPR to avoid introducing trees that the template
processing can't handle well.  This I achieved by adding a wrapper
function.

gcc/cp/ChangeLog:

	PR c++/95789
	PR c++/96104
	PR c++/96179
	* call.c (convert_like_real_1): Renamed from convert_like_real.
	(convert_like_real): New wrapper for convert_like_real_1.

gcc/testsuite/ChangeLog:

	PR c++/95789
	PR c++/96104
	PR c++/96179
	* g++.dg/conversion/ref4.C: New test.
	* g++.dg/conversion/ref5.C: New test.
	* g++.dg/conversion/ref6.C: New test.

(cherry picked from commit 8e64d182850560dbedfabb88aac90d4fc6155067)

The version of nvprof in CUDA 9.0 causes a hang when used to profile an
OpenACC program.  This is because it calls acc_get_device_type from
a callback called during device initialization, which then attempts
to acquire acc_device_lock while it is already taken, resulting in
deadlock.  This works around the issue by returning acc_device_none
from acc_get_device_type without attempting to acquire the lock when
initialization has not completed yet.

2020-07-14  Tom de Vries  <tom@codesourcery.com>
	    Cesar Philippidis  <cesar@codesourcery.com>
	    Thomas Schwinge  <thomas@codesourcery.com>
	    Kwok Cheung Yeung  <kcy@codesourcery.com>

	libgomp/
	* oacc-init.c (acc_init_state_lock, acc_init_state, acc_init_thread):
	New variable.
	(acc_init_1): Set acc_init_thread to pthread_self ().  Set
	acc_init_state to initializing at the start, and to initialized at the
	end.
	(self_initializing_p): New function.
	(acc_get_device_type): Return acc_device_none if called by thread that
	is currently executing acc_init_1.
	* libgomp.texi (acc_get_device_type): Update documentation.
	(Implementation Status and Implementation-Defined Behavior): Likewise.
	* testsuite/libgomp.oacc-c-c++-common/acc_prof-init-2.c: New.

(cherry picked from commit b52643ab9004ba8ecea06a399885fe1e04183eda)

The testcase has failed since r9-5035, because obj_type_ref_class
tries to look up an ODR type when no ODR type information is
available.  (The information was available earlier in the
compilation, but was freed during pass_ipa_free_lang_data.)
We then crash dereferencing the null get_odr_type result.

The test passes with -O2.  However, it fails again if -fdump-tree-all
is used, since obj_type_ref_class is called indirectly from the
dump routines.

Other code creates ODR type entries on the fly by passing “true”
as the insert parameter.  But obj_type_ref_class can't do that
unconditionally, since it should have no side-effects when used
from the dumping code.

Following a suggestion from Honza, this patch adds parameters
to say whether the routines are being called from dump routines
and uses those to derive the insert parameter.

gcc/
	PR middle-end/95114
	* tree.h (virtual_method_call_p): Add a default-false parameter
	that indicates whether the function is being called from dump
	routines.
	(obj_type_ref_class): Likewise.
	* tree.c (virtual_method_call_p): Likewise.
	* ipa-devirt.c (obj_type_ref_class): Likewise.  Lazily add ODR
	type information for the type when the parameter is false.
	* tree-pretty-print.c (dump_generic_node): Update calls to
	virtual_method_call_p and obj_type_ref_class accordingly.

gcc/testsuite/
	PR middle-end/95114
	* g++.target/aarch64/pr95114.C: New test.

The range infrastructure has code to decompose POLY_INT_CST ranges
to worst-case integer bounds.  However, it had the fundamental flaw
(obvious in hindsight) that it applied to anti-ranges too, meaning
that a range 2+2X would end up with a range of ~[2, +INF], i.e.
[-INF, 1].  This patch decays to varying in that case instead.

I'm still a bit uneasy about this.  ISTM that in terms of
generality:

  SSA_NAME => POLY_INT_CST => INTEGER_CST
           => ADDR_EXPR

I.e. an SSA_NAME could store a POLY_INT_CST and a POLY_INT_CST
could store an INTEGER_CST (before canonicalisation).  POLY_INT_CST
is also “as constant as” ADDR_EXPR (well, OK, only some ADDR_EXPRs
are run-time rather than link-time constants, whereas all POLY_INT_CSTs
are, but still).  So it seems like we should at least be able to treat
POLY_INT_CST as symbolic.  On the other hand, I don't have any examples
in which that would be useful.

gcc/
	PR tree-optimization/96146
	* value-range.cc (value_range::set): Only decompose POLY_INT_CST
	bounds to integers for VR_RANGE.  Decay to VR_VARYING for anti-ranges
	involving POLY_INT_CSTs.

gcc/testsuite/
	PR tree-optimization/96146
	* gcc.target/aarch64/sve/acle/general/pr96146.c: New test.

> > The store to the whole of each volatile object was picked apart
> > like there had been an individual assignment to each of the
> > fields.  Reads were added as part of that; see PR for details.
> > The reads from volatile memory were a clear bug; individual
> > stores questionable.  A separate patch clarifies the docs.

This breaks building of mesa on both the trunk and 10 branch.

The problem is that the middle-end may never create temporaries of non-POD
(TREE_ADDRESSABLE) types, those can be only created when the language says
so and thus only the FE is allowed to create those.

This patch just reverts the behavior to what we used to do before for the
stores to volatile non-PODs.  Perhaps we want to do something else, but
definitely we can't create temporaries of the non-POD type.  It is up to
discussions on what should happen in those cases.

2020-07-14  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/96194
	* expr.c (expand_constructor): Don't create temporary for store to
	volatile MEM if exp has an addressable type.

	* g++.dg/opt/pr96194.C: New test.

(cherry picked from commit b1d389d60d1929c7528ef984925ea010e3bf2c1a)

2020-07-14  Matthias Klose  <doko@ubuntu.com>

	PR lto/95604
	* lto-wrapper.c (merge_and_complain): Add decoded options as parameter,
	error on different values for -fcf-protection.
	(append_compiler_options): Pass -fcf-protection option.
	(find_and_merge_options): Add decoded options as parameter,
	pass decoded_options to merge_and_complain.
	(run_gcc): Pass decoded options to find_and_merge_options.
	* lto-opts.c (lto_write_options): Pass -fcf-protection option.

(cherry picked from commit 6a48d12475cdb7375b98277f8bc089715feeeafe)

Because the check for power10_hw is not called
check_effective_target_power10_hw, it needs to be looked
for by is-effective-target-keyword. Also reorder things
in is-effective-target to put power10_hw with the other
ppc stuff.

2020-07-13  Aaron Sawdey  <acsawdey@linux.ibm.com>

gcc/testsuite/

	* lib/target-supports.exp (is-effective-target):
	Reorder to put powerpc stuff together.
	(is-effective-target-keyword): Add power10_hw.

(cherry picked from commit 94c7c67b82dd7255fde0d7ae42d483336ea1b60b)

Add a test for dejagnu to determine if execution of MMA instructions is
supported in the test environment. Add an execution test to make sure
that __builtin_cpu_supports("mma") is true if we can execute MMA
instructions.

2020-07-13  Aaron Sawdey  <acsawdey@linux.ibm.com>

gcc/testsuite/

	* lib/target-supports.exp (check_ppc_mma_hw_available):
	New function.
	(is-effective-target): Add ppc_mma_hw.
	(is-effective-target-keyword): Add ppc_mma_hw.
	* gcc.target/powerpc/mma-supported.c: New file.
	* gcc.target/powerpc/mma-single-test.c: Require ppc_mma_hw.
	* gcc.target/powerpc/mma-double-test.c: Require ppc_mma_hw.

(cherry picked from commit 305ab735bd40b52a451851fa6e2177f184eb05d4)

Define the __ARM_FEATURE_PAC_DEFAULT feature test
macro when PAC-RET branch protection is enabled.

2020-07-13  Szabolcs Nagy  <szabolcs.nagy@arm.com>

gcc/ChangeLog:

	* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add
	__ARM_FEATURE_PAC_DEFAULT support.

(cherry picked from commit a1faa8e2470b33e92f6274804bf7941fbb6e2d38)

The expected semantics and valid usage of __builtin_return_address is
not clear since it exposes implementation internals that are normally
not meaningful to portable c code.

This documentation change tries to clarify the semantics in case the
return address is stored in a mangled form. This affects AArch64 when
pointer authentication is used for the return address signing (i.e.
-mbranch-protection=pac-ret).

2020-07-13  Szabolcs Nagy  <szabolcs.nagy@arm.com>

gcc/ChangeLog:

	PR target/94891
	* doc/extend.texi: Update the text for  __builtin_return_address.

(cherry picked from commit 6a391e06f953c3390b14020d8cacb6d55f81b2b9)

Mangling, currently only used on AArch64 for return address signing,
is an internal representation that should not be exposed via

  __builtin_return_address return value,
  __builtin_eh_return handler argument,
  _Unwind_DebugHook handler argument.

Note that a mangled address might not even fit into a void *, e.g.
with AArch64 ilp32 ABI the return address is stored as 64bit, so
the mangled return address cannot be accessed via _Unwind_GetPtr.

This patch changes the unwinder hooks as follows:

MD_POST_EXTRACT_ROOT_ADDR is removed: root address comes from
__builtin_return_address which is not mangled.

MD_POST_EXTRACT_FRAME_ADDR is renamed to MD_DEMANGLE_RETURN_ADDR,
it now operates on _Unwind_Word instead of void *, so the hook
should work when return address signing is enabled on AArch64 ilp32.
(But for that __builtin_aarch64_autia1716 should be fixed to operate
on 64bit input instead of a void *.)

MD_POST_FROB_EH_HANDLER_ADDR is removed: it is the responsibility of
__builtin_eh_return to do the mangling if necessary.

2020-07-13  Szabolcs Nagy  <szabolcs.nagy@arm.com>

libgcc/ChangeLog:

	PR target/94891
	* config/aarch64/aarch64-unwind.h (MD_POST_EXTRACT_ROOT_ADDR): Remove.
	(MD_POST_FROB_EH_HANDLER_ADDR): Remove.
	(MD_POST_EXTRACT_FRAME_ADDR): Rename to ...
	(MD_DEMANGLE_RETURN_ADDR): This.
	(aarch64_post_extract_frame_addr): Rename to ...
	(aarch64_demangle_return_addr): This.
	(aarch64_post_frob_eh_handler_addr): Remove.
	* unwind-dw2.c (uw_update_context): Demangle return address.
	(uw_frob_return_addr): Remove.

(cherry picked from commit b097c7a27fb0796b2653a1d003cbf6b7a69d8961)

Currently __builtin_eh_return takes a signed return address, which can
cause ABI and API issues: 1) pointer representation problems if the
address is passed around before eh return, 2) the source code needs
pac-ret specific changes and needs to know if pac-ret is used in the
current frame, 3) signed address may not be representible as void *
(with ilp32 abi).

Using address signing to protect eh return is ineffective because the
instruction sequence in the unwinder that starts from the address
signing and ends with a ret can be used as a return to anywhere gadget.
Using indirect branch istead of ret with bti j landing pads at the
target can reduce the potential of such gadget, which also implies
that __builtin_eh_return should not take a signed address.

This is a big hammer fix to the ABI and API issues: it turns pac-ret
off for the caller completely (not just on the eh return path).  To
harden the caller against ROP attacks, it should use indirect branch
instead of ret, this is not attempted so the patch remains small and
backportable.

2020-07-13  Szabolcs Nagy  <szabolcs.nagy@arm.com>

gcc/ChangeLog:

	PR target/94891
	* config/aarch64/aarch64.c (aarch64_return_address_signing_enabled):
	Disable return address signing if __builtin_eh_return is used.

gcc/testsuite/ChangeLog:

	PR target/94891
	* gcc.target/aarch64/return_address_sign_1.c: Update test.
	* gcc.target/aarch64/return_address_sign_b_1.c: Likewise.

(cherry picked from commit 2bc95be3bb8c8138e2e87c1c11c84bfede989d61)

This is a big hammer fix for __builtin_return_address (PR target/94891)
returning signed addresses (sometimes, depending on wether lr happens
to be signed or not at the time of call which depends on optimizations),
and similarly -pg may pass signed return address to _mcount
(PR target/94791).

At the time of return address expansion we don't know if it's signed or
not so it is done unconditionally.

2020-07-13  Szabolcs Nagy  <szabolcs.nagy@arm.com>

gcc/ChangeLog:

	PR target/94891
	PR target/94791
	* config/aarch64/aarch64-protos.h (aarch64_return_addr_rtx): Declare.
	* config/aarch64/aarch64.c (aarch64_return_addr_rtx): New.
	(aarch64_return_addr): Use aarch64_return_addr_rtx.
	* config/aarch64/aarch64.h (PROFILE_HOOK): Likewise.

(cherry picked from commit 463a54e5d4956143f81c1f23b91cbd2d93855741)

sjlj.S did not have the GNU property note markup and the BTI c
instructions that are necessary when it is built with branch
protection.

The notes are only added when libitm is built with branch
protection, because old linkers mishandle the note (merge
them incorrectly or emit warnings), the BTI instructions
are added unconditionally.

2020-07-09  Szabolcs Nagy  <szabolcs.nagy@arm.com>

libitm/ChangeLog:

	* config/aarch64/sjlj.S: Add BTI marking and related definitions,
	and add BTI c to function entries.

(cherry picked from commit 319078dad62eba942d33c8975bdcbb09d1c68ba6)

lse.S did not have the GNU property note markup and the BTI c
instructions that are necessary when it is built with branch
protection.

The notes are only added when libgcc is built with branch
protection, because old linkers mishandle the note (merge
them incorrectly or emit warnings), the BTI instructions
are added unconditionally.

Note: BTI c is only necessary at function entry if the function
may be called indirectly, currently lse functions are not called
indirectly, but BTI is added for ABI reasons e.g. to allow
linkers later to emit stub code with indirect jump.

2020-07-09  Szabolcs Nagy  <szabolcs.nagy@arm.com>

libgcc/ChangeLog:

	PR target/96001
	* config/aarch64/lse.S: Add BTI marking and related definitions,
	and add BTI c to function entries.

(cherry picked from commit f0f62fa0320762119446893c67cb52934bc5a05e)

lse.S did not have GNU stack note, this may cause missing
PT_GNU_STACK in binaries on Linux and FreeBSD.

2020-07-09  Szabolcs Nagy  <szabolcs.nagy@arm.com>

libgcc/ChangeLog:

	* config/aarch64/lse.S: Add stack note.

(cherry picked from commit e73ec755489afc9fcc75dfac6f06ac73e243e72a)

sjlj.S only had the note on Linux, but it is supposed
to have it on FreeBSD too.

2020-07-09  Szabolcs Nagy  <szabolcs.nagy@arm.com>

libitm/ChangeLog:

	* config/aarch64/sjlj.S: Add stack note if __FreeBSD__ is defined.

(cherry picked from commit 463ba375f7b857995068403a4c63690d03162c00)

Define the __ARM_FEATURE_BTI_DEFAULT feature test
macro when BTI branch protection is enabled.

2020-07-09  Szabolcs Nagy  <szabolcs.nagy@arm.com>

gcc/ChangeLog:

	* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add
	__ARM_FEATURE_BTI_DEFAULT support.

(cherry picked from commit 63b6808e69699ba576492efa29d92b626cc26eba)