PR lto/83954
	* lto-symtab.c (warn_type_compatibility_p): Do not recurse into the
	component type of array types with non-aliased component.

From-SVN: r257343

       * config/powerpcspe/powerpcspe.opt: Add Undocumented to irrelevant
       options.
       * config/powerpcspe/powerpcspe-tables.opt (rs6000_cpu_opt_value):
       Remove all values except native, 8540 and 8548.

From-SVN: r257342

	* config/i386/i386.c (ix86_output_function_return): Pass
	INVALID_REGNUM, instead of -1, as invalid register number to
	indirect_thunk_name and output_indirect_thunk.

From-SVN: r257340

	* tree.c (strip_typedefs_expr): Use cp_tree_operand_length.

From-SVN: r257339

	* gfortran.dg/dec_parameter_1.f (sub1): Remove statement with no effect.
	* gfortran.dg/dec_parameter_2.f90 (sub1): Ditto.

From-SVN: r257337

[testsuite]

2018-02-02  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* gcc.target/powerpc/vec-cmpne-long.c: Add p8vector_hw require to
	dg-do run stanza.

From-SVN: r257336

[testsuite]

2018-01-31  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* gcc.target/powerpc/fold-vec-abs-int.p9.c: Add powerpc_p9vector_ok
	requirement.
	* gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c: Same.
	* gcc.target/powerpc/fold-vec-cmp-char.p9.c: Same.
	* gcc.target/powerpc/fold-vec-neg-int.p9.c: Same.

From-SVN: r257335

	* go-gcc.cc (Gcc_backend::type_size): Return 0 for
	void_type_node.
	(Gcc_backend::convert_expression): Don't convert if the type of
	expr_tree is void_type_node.
	(Gcc_backend::array_index_expression): Don't index if the type of
	the array expression is void_type_node.
	(Gcc_backend::init_statement): Don't initialize if the type of the
	initializer expression is void_type_node.
	(Gcc_backend::assignment_statement): Don't assign if the type of
	either the left or right hand side is void_type_node.
	(Gcc_backend::temporary_variable): Don't initialize if the type of
	the initializer expression is void_type_node.

From-SVN: r257334

	PR testsuite/52641
	* gcc.c-torture/execute/pr83362.c: Make work for int16.
	* gcc.dg/Wsign-conversion.c: Dito.
	* gcc.dg/attr-alloc_size-4.c: Dito.
	* gcc.dg/pr81020.c: Dito.
	* gcc.dg/pr81192.c: Dito.
	* gcc.dg/pr83463.c (dg-options): Add -Wno-pointer-to-int-cast.
	* gcc.dg/attr-alloc_size-11.c: Also special-case avr.
	* gcc.dg/pr83844.c: Restrict to int32plus.
	* gcc.dg/attr-alloc_size-3.c: Restrict to size32plus.
	* gcc.dg/tree-ssa/ldist-25.c: Dito.
	* gcc.dg/tree-ssa/ldist-27.c: Dito.
	* gcc.dg/tree-ssa/ldist-28.c: Dito.
	* gcc.dg/tree-ssa/ldist-29.c: Dito.
	* gcc.dg/tree-ssa/ldist-30.c: Dito.
	* gcc.dg/tree-ssa/ldist-31.c: Dito.
	* gcc.dg/tree-ssa/ldist-32.c: Dito.
	* gcc.dg/tree-ssa/ldist-33.c: Dito.
	* gcc.dg/tree-ssa/ldist-34.c: Dito.
	* gcc.dg/tree-ssa/ldist-35.c: Dito.
	* gcc.dg/tree-ssa/ldist-36.c: Dito.

From-SVN: r257333

gcc/
	* config.gcc: Add -march=icelake.
	* config/i386/driver-i386.c (host_detect_local_cpu): Detect icelake.
	* config/i386/i386-c.c (ix86_target_macros_internal): Handle icelake.
	* config/i386/i386.c (processor_costs): Add m_ICELAKE.
	(PTA_ICELAKE, PTA_AVX512VNNI, PTA_GFNI, PTA_VAES, PTA_AVX512VBMI2,
	PTA_VPCLMULQDQ, PTA_RDPID, PTA_AVX512BITALG): New.
	(processor_target_table): Add icelake.
	(ix86_option_override_internal): Handle new PTAs.
	(get_builtin_code_for_version): Handle icelake.
	(M_INTEL_COREI7_ICELAKE): New.
	(fold_builtin_cpu): Handle icelake.
	* config/i386/i386.h (TARGET_ICELAKE, PROCESSOR_ICELAKE): New.
	* doc/invoke.texi: Add -march=icelake.
gcc/testsuite/
	* gcc.target/i386/funcspec-56.inc: Handle new march.
	* g++.dg/ext/mv16.C: Ditto.
libgcc/
	* config/i386/cpuinfo.h (processor_subtypes): Add INTEL_COREI7_ICELAKE.

From-SVN: r257331

    
    The language spec says that in `for i = range x`, in which there is no
    second iteration variable, if len(x) is constant, then x is not
    evaluated.  This only matters when x is an expression that panics but
    whose type is an array type; in such a case, we should not evaluate x,
    since len of any array type is a constant.
    
    Fixes golang/go#22313
    
    Reviewed-on: https://go-review.googlesource.com/91555

From-SVN: r257330

gcc/c-family/
	* c-common.h (omp_clause_mask): Move to wide_int_bitmask.h.

gcc/
	* config/i386/i386.c (ix86_option_override_internal): Change flags type
	to wide_int_bitmask.
	* wide-int-bitmask.h: New.

From-SVN: r257329

	* lib/target-supports.exp
	(check_effective_target_keeps_null_pointer_checks): No more
	special-case avr.
	* gcc.dg/tree-ssa/pr21086.c (dg-final): Special-case avr.
	* gcc.dg/ifcvt-4.c: Skip avr.
	* gcc.dg/pr53037-1.c: Dito.
	* gcc.dg/pr53037-2.c: Dito.
	* gcc.dg/pr53037-3.c: Dito.
	* gcc.dg/pr63387-2.c: Dito.
	* gcc.dg/pr63387.c: Dito.
	* gcc.dg/sancov/cmp0.c: Dito.
	* gcc.dg/tree-ssa/loop-interchange-1.c: Dito.
	* gcc.dg/tree-ssa/loop-interchange-10.c: Dito.
	* gcc.dg/tree-ssa/loop-interchange-11.c: Dito.
	* gcc.dg/tree-ssa/loop-interchange-1b.c: Dito.
	* gcc.dg/tree-ssa/loop-interchange-2.c: Dito.
	* gcc.dg/tree-ssa/loop-interchange-3.c: Dito.
	* gcc.dg/tree-ssa/loop-interchange-4.c: Dito.
	* gcc.dg/tree-ssa/loop-interchange-5.c: Dito.
	* gcc.dg/tree-ssa/loop-interchange-6.c: Dito.
	* gcc.dg/tree-ssa/loop-interchange-7.c: Dito.
	* gcc.dg/tree-ssa/loop-interchange-8.c: Dito.
	* gcc.dg/tree-ssa/loop-interchange-9.c: Dito.
	* gcc.dg/tree-ssa/pr82059.c: Dito.
	* gcc.c-torture/execute/pr70460.c: Dito.

From-SVN: r257328

	PR testsuite/52641
	* gcc.c-torture/execute/pr81913.c: Use types that also work for int16.
	* gcc.c-torture/execute/20180112-1.c: Dito.
	* gcc.c-torture/execute/pr81503.c: Dito.
	* gcc.dg/store_merging_12.c: Dito.
	* gcc.dg/tree-ssa/loop-niter-1.c: Dito.
	* gcc.dg/tree-ssa/loop-niter-2.c: Dito.
	* gcc.dg/tree-ssa/pr80898.c: Dito.
	* gcc.dg/tree-ssa/pr82363.c: Dito.
	* gcc.dg/utf16-4.c: Also allow "short unsigned int" in dg-warning.
	* gcc.dg/tree-ssa/pr81346-5.c: Special-case int16.
	* gcc.dg/tree-ssa/ssa-sink-11.c: Dito.
	* gcc.dg/tree-ssa/ssa-sink-12.c: Dito.
	* gcc.dg/torture/pr81814.c: Restrict to int32plus.
	* gcc.dg/tree-ssa/pr80803.c: Dito.
	* gcc.dg/tree-ssa/pr80898-2.c: Dito.
	* gcc.dg/tree-ssa/pr81346-4.c: Dito.
	* gcc.dg/tree-ssa/vrp114.c: Dito.
	* gcc.dg/tree-ssa/pr82574.c: Restrict to size32plus.
	* gcc.dg/tree-ssa/ssa-dom-thread-13.c: Dito.
	* gcc.dg/tree-ssa/ssa-sink-15.c: Dito.

From-SVN: r257327

x32 is a 64-bit process with 32-bit software pointer and kernel may
place x32 shadow stack above 4GB.  We need to save and restore 64-bit
shadow stack register for x32. builtin jmp buf size is 5 pointers.  We
have space to save 64-bit shadow stack pointers: 32-bit SP, 32-bit FP,
32-bit IP, 64-bit SSP for x32.

	PR target/84066
	* gcc/config/i386/i386.md: Replace Pmode with word_mode in
	builtin_setjmp_setup and builtin_longjmp to support x32.
	* gcc/testsuite/gcc.target/i386/cet-sjlj-6a.c: New test.
	* gcc/testsuite/gcc.target/i386/cet-sjlj-6b.c: Likewise.

From-SVN: r257326

	* lambda.c (is_capture_proxy_with_ref): New.
	(insert_capture_proxy): Don't set DECL_CAPTURED_VARIABLE from a
	COMPONENT_REF.
	* expr.c (mark_use): Use is_capture_proxy_with_ref.
	* constexpr.c (potential_constant_expression_1): Likewise.
	* semantics.c (process_outer_var_ref): Likewise.

From-SVN: r257325

    
    They were disabled due to the lack of escape analysis. Now that
    we have escape analysis, unskip these tests.
    
    Reviewed-on: https://go-review.googlesource.com/86248

From-SVN: r257324

    
    On ia64, a separate stack is used for saving/restoring register frames,
    occupying the other end of the stack mapping. This must also be scanned
    for pointers into the heap.
    
    Reviewed-on: https://go-review.googlesource.com/85276

From-SVN: r257323

From-SVN: r257322

    
    The escape analysis now runs by default. It can be disabled with
    the negative flag, -fno-go-optimize-allocs.
    
    Reviewed-on: https://go-review.googlesource.com/86247

	* lang.opt (fgo-optimize): Remove RejectNegative.
	* go-c.h (go_enable_optimize): Update declaration to take value
	argument.
	* go-lang.c (go_langhook_handle_option): Pass value to
	go_enable_optimize.
	* gccgo.texi (Invoking gccgo): Update -fgo-optimize-allocs doc.

From-SVN: r257319

From-SVN: r257313

    
    We were using special compilation flags for the math package, but we
    weren't using them when testing.  That meant that our tests were not
    checking the real code we were providing.  Fix that.
    
    Fixing that revealed that we were not using a good set of flags, or at
    least were not using flags that let the tests pass.  Adjust the flags
    to stop using -funsafe-math-optimizations on x86.  Instead always use
    -ffp-contract=off -fno-math-errno -fno-trapping-math for all targets.
    
    Fixes golang/go#23647
    
    Reviewed-on: https://go-review.googlesource.com/91355

From-SVN: r257312

	PR c++/84125
	* typeck.c (build_address): Relax the assert when
	processing_template_decl.

	* g++.dg/cpp1y/lambda-generic-84125.C:New test.

From-SVN: r257311

When associating a variable of type character, if the length of the
target isn't known at compile time, generate an error. See PR 83344
for more details.

Regtested on x86_64-pc-linux-gnu.

gcc/fortran/ChangeLog:

2018-02-01  Janne Blomqvist  <jb@gcc.gnu.org>

	PR 83975
	PR 83344
	* resolve.c (resolve_assoc_var): Generate an error if
	target length unknown.

From-SVN: r257310

	PR c++/84036
	PR c++/82249
	* pt.c (tsubst_pack_expansion): Handle function parameter_packs in
	PACK_EXPANSION_EXTRA_ARGS.

From-SVN: r257307

	PR target/56010
	PR target/83743
	* config/rs6000/driver-rs6000.c: #include "diagnostic.h".
	#include "opts.h".
	(rs6000_supported_cpu_names): New static variable.
	(linux_cpu_translation_table): Likewise.
	(elf_platform) <cpu>: Define new static variable and use it.
	Translate kernel AT_PLATFORM name to canonical name if needed.
	Error if platform name is unknown.

From-SVN: r257305

re PR middle-end/84089 (FAIL: g++.dg/cpp1y/lambda-generic-x.C  -std=gnu++14 (internal compiler error))

	PR target/84089
	* config/pa/predicates.md (base14_operand): Handle E_VOIDmode.

From-SVN: r257304

	PR target/84128
	* config/i386/i386.c (release_scratch_register_on_entry): Add new
	OFFSET and RELEASE_VIA_POP arguments.  Use SP+OFFSET to restore
	the scratch if RELEASE_VIA_POP is false.
	(ix86_adjust_stack_and_probe_stack_clash): Un-constify SIZE.
	If we have to save a temporary register, decrement SIZE appropriately.
	Pass new arguments to release_scratch_register_on_entry.
	(ix86_adjust_stack_and_probe): Likewise.
	(ix86_emit_probe_stack_range): Pass new arguments to
	release_scratch_register_on_entry.

	PR target/84128
	* gcc.target/i386/pr84128.c: New test.

From-SVN: r257303

	PR rtl-optimization/84157
	* combine.c (change_zero_ext): Use REG_P predicate in
	front of HARD_REGISTER_P predicate.

From-SVN: r257302

gcc/
	* config/avr/avr.c (avr_option_override): Move disabling of
	-fdelete-null-pointer-checks to...
	* common/config/avr/avr-common.c (avr_option_optimization_table):
	...here.
testsuite/
	* gcc.dg/tree-ssa/vrp111.c (dg-options): Add
	-fdelete-null-pointer-checks.

From-SVN: r257301

    
    This matches the gc compiler.
    
    The test case was sent for the master repo as
    https://golang.org/cl/91138.
    
    Fixes golang/go#23620
    
    Reviewed-on: https://go-review.googlesource.com/91139

From-SVN: r257300

    
    Otherwise on a 64-bit system we will read the 32-bit value as a 64-bit
    value.  Since getaddrinfo returns negative numbers as error values,
    these will be interpreted as numbers like 0xfffffffe rather than -2,
    and the comparisons with values like syscall.EAI_NONAME will fail.
    
    Fixes golang/go#23645
    
    Reviewed-on: https://go-review.googlesource.com/91296

From-SVN: r257299

re PR c++/83796 (Abstract classes allowed to be instantiated when initialised as default parameter to function or constructor)

/cp
2018-02-01  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/83796
	* call.c (convert_like_real): If w're initializing from {} explicitly
	call abstract_virtuals_error_sfinae.

/testsuite
2018-02-01  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/83796
	* g++.dg/cpp0x/abstract-default1.C: New.

From-SVN: r257298

This patch implements the original suggestion for fixing PR 81635:
use range info in split_constant_offset to see whether a conversion
of a wrapping type can be split.  The range info problem described in:

    https://gcc.gnu.org/ml/gcc-patches/2017-08/msg01002.html

seems to have been fixed.

The patch is part 1.  There needs to be a follow-on patch to handle:

  for (unsigned int i = 0; i < n; i += 4)
    {
      ...[i + 2]...
      ...[i + 3]...

which the old SCEV test handles, but which the range check doesn't.
At the moment we record that the low two bits of "i" are clear,
but we still end up with a maximum range of 0xffffffff rather than
0xfffffffc.

2018-01-31  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	PR tree-optimization/81635
	* tree-data-ref.c (split_constant_offset_1): For types that
	wrap on overflow, try to use range info to prove that wrapping
	cannot occur.

gcc/testsuite/
	PR tree-optimization/81635
	* gcc.dg/vect/bb-slp-pr81635-1.c: New test.
	* gcc.dg/vect/bb-slp-pr81635-2.c: Likewise.

From-SVN: r257296

In aarch64 backend, ip0/ip1 register will be used in the prologue/epilogue as
temporary register.

When the compiler is performing sibcall optimization. It has the chance to use
ip0/ip1 register for indirect function call to hold the address. However,
those two register might be clobbered by the epilogue code which makes the
last sibcall instruction invalid.

The patch here renames the register class CALLER_SAVE_REGS to TAILCALL_ADDR_REGS
to reflect its usage, and remove IP registers from this class.

gcc/

2018-02-01  Renlin Li  <renlin.li@arm.com>

	PR target/83370
	* config/aarch64/aarch64.c (aarch64_class_max_nregs): Handle
	TAILCALL_ADDR_REGS.
	(aarch64_register_move_cost): Likewise.
	* config/aarch64/aarch64.h (reg_class): Rename CALLER_SAVE_REGS to
	TAILCALL_ADDR_REGS.
	(REG_CLASS_NAMES): Likewise.
	(REG_CLASS_CONTENTS): Rename CALLER_SAVE_REGS to
	TAILCALL_ADDR_REGS. Remove IP registers.
	* config/aarch64/aarch64.md (Ucs): Update register constraint.

gcc/testsuite/

2018-02-01  Richard Sandiford  <richard.sandiford@linaro.org>

	PR target/83370
	* gcc.target/aarch64/pr83370.c: New.

From-SVN: r257294

domwalk.h (dom_walker::dom_walker): Add additional constructor for specifying RPO order and allow NULL for that.

2018-02-01  Richard Biener  <rguenther@suse.de>

	* domwalk.h (dom_walker::dom_walker): Add additional constructor
	for specifying RPO order and allow NULL for that.
	* domwalk.c (dom_walker::dom_walker): Likewise.
	(dom_walker::walk): Handle NULL RPO order.
	* tree-into-ssa.c (rewrite_dom_walker): Do not walk dom children
	in RPO order.
	(rewrite_update_dom_walker): Likewise.
	(mark_def_dom_walker): Likewise.

	* gcc.dg/graphite/pr35356-1.c: Adjust.

From-SVN: r257293

The SVE tests are split into code-quality compile tests and runtime
tests.  A lot of the former are geared towards LP64.  It would be
possible (but tedious!) to mark up every line that is expected to work
only for LP64, but I think it would be a constant source of problems.

Since the code has not been tuned for ILP32 yet, I think the best
thing is to select only the runtime tests for that combination.
They all pass on aarch64-elf and aarch64_be-elf except vec-cond-[34].c,
which are unsupported due to the lack of fenv support.

The patch also replaces uses of built-in types with stdint.h types
where possible.  (This excludes tests that change the endianness,
since we can't assume that system header files work in that case.)

2018-02-01  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/testsuite/
	PR testsuite/83846
	* gcc.target/aarch64/sve/aarch64-sve.exp: Only do *_run tests
	for ILP32.
	* gcc.target/aarch64/sve/clastb_2_run.c (main): Use TYPE instead
	of hard-coding the choice.
	* gcc.target/aarch64/sve/clastb_4_run.c (main): Likewise.
	* gcc.target/aarch64/sve/clastb_5_run.c (main): Likewise.
	* gcc.target/aarch64/sve/clastb_3_run.c (main): Likewise.  Generalize
	memset call.
	* gcc.target/aarch64/sve/const_pred_1.C: Include stdint.h and use
	stdint.h types.
	* gcc.target/aarch64/sve/const_pred_2.C: Likewise.
	* gcc.target/aarch64/sve/const_pred_3.C: Likewise.
	* gcc.target/aarch64/sve/const_pred_4.C: Likewise.
	* gcc.target/aarch64/sve/load_const_offset_2.c: Likewise.
	* gcc.target/aarch64/sve/logical_1.c: Likewise.
	* gcc.target/aarch64/sve/mask_struct_load_1.c: Likewise.
	* gcc.target/aarch64/sve/mask_struct_load_2.c: Likewise.
	* gcc.target/aarch64/sve/mask_struct_load_3.c: Likewise.
	* gcc.target/aarch64/sve/mask_struct_load_4.c: Likewise.
	* gcc.target/aarch64/sve/mask_struct_load_5.c: Likewise.
	* gcc.target/aarch64/sve/mask_struct_load_6.c: Likewise.
	* gcc.target/aarch64/sve/mask_struct_load_7.c: Likewise.
	* gcc.target/aarch64/sve/mask_struct_load_8.c: Likewise.
	* gcc.target/aarch64/sve/mask_struct_store_1.c: Likewise.
	* gcc.target/aarch64/sve/mask_struct_store_2.c: Likewise.
	* gcc.target/aarch64/sve/mask_struct_store_3.c: Likewise.
	* gcc.target/aarch64/sve/mask_struct_store_4.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_1.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_2.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_2_run.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_3.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_3_run.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_4.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_4_run.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_7.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_8.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_8_run.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_9.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_9_run.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_10.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_10_run.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_11.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_11_run.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_12.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_12_run.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_13.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_13_run.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_14.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_18.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_19.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_20.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_21.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_22.c: Likewise.
	* gcc.target/aarch64/sve/struct_vect_23.c: Likewise.
	* gcc.target/aarch64/sve/popcount_1.c (popcount_64): Use
	__builtin_popcountll rather than __builtin_popcountl.

Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>

From-SVN: r257290

Subreg reads should be equivalent to storing the inner register to
memory and loading the appropriate memory bytes back, with subreg
writes doing the reverse.  For the reasons explained in the comments,
this isn't what happens for big-endian SVE if we simply reinterpret
one vector register as having a different element size, so the
conceptual store and load is needed in the general case.

However, that obviously produces poor code if we do it too often.
The patch therefore adds a pattern for handling the operation in
registers.  This copes with the important case of a VIEW_CONVERT
created by tree-vect-slp.c:duplicate_and_interleave.

It might make sense to tighten the predicates in aarch64-sve.md so
that such subregs are not allowed as operands to most instructions,
but that's future work.

This fixes the sve/slp_*.c tests on aarch64_be.

2018-02-01  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	* config/aarch64/aarch64-protos.h (aarch64_split_sve_subreg_move)
	(aarch64_maybe_expand_sve_subreg_move): Declare.
	* config/aarch64/aarch64.md (UNSPEC_REV_SUBREG): New unspec.
	* config/aarch64/predicates.md (aarch64_any_register_operand): New
	predicate.
	* config/aarch64/aarch64-sve.md (mov<mode>): Optimize subreg moves
	that are semantically a reverse operation.
	(*aarch64_sve_mov<mode>_subreg_be): New pattern.
	* config/aarch64/aarch64.c (aarch64_maybe_expand_sve_subreg_move):
	(aarch64_replace_reg_mode, aarch64_split_sve_subreg_move): New
	functions.
	(aarch64_can_change_mode_class): For big-endian, forbid changes
	between two SVE modes if they have different element sizes.

Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>

From-SVN: r257289

This patch deals with cases in which a CONST_VECTOR contains a
repeating bit pattern that is wider than one element but narrower
than 128 bits.  The current code:

* treats the repeating pattern as a single element
* uses the associated LD1R to load and replicate it (such as LD1RD
  for 64-bit patterns)
* uses a subreg to cast the result back to the original vector type

The problem is that for big-endian targets, the final cast is
effectively a form of element reverse.  E.g. say we're using LD1RD to load
16-bit elements, with h being the high parts and l being the low parts:

                               +-----+-----+-----+-----+-----+----
                         lanes |  0  |  1  |  2  |  3  |  4  | ...
                               +-----+-----+-----+-----+-----+----
     memory              bytes |h0 l0 h1 l1 h2 l2 h3 l3 h0 l0 ....
                               +----------------------------------
                                 V  V  V  V  V  V  V  V
                     ----------+-----------------------+
    register         ....      |           0           |
     after           ----------+-----------------------+  lsb
     LD1RD           .... h3 l3 h0 l0 h1 l1 h2 l2 h3 l3|
                     ----------------------------------+

                     ----+-----+-----+-----+-----+-----+
    expected         ... |  4  |  3  |  2  |  1  |  0  |
    register         ----+-----+-----+-----+-----+-----+  lsb
    contents         .... h0 l0 h3 l3 h2 l2 h1 l1 h0 l0|
                     ----------------------------------+

A later patch fixes the handling of general subregs to account
for this, but it means that we need to do a REV instruction
after the load.  It seems better to use LD1RQ[BHW] on a 128-bit
pattern instead, since that gets the endianness right without
a separate fixup instruction.

2018-02-01  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	* config/aarch64/aarch64.c (aarch64_expand_sve_const_vector): Prefer
	the TImode handling for big-endian targets.

gcc/testsuite/
	* gcc.target/aarch64/sve/slp_2.c: Expect LD1RQ to be used instead
	of LD1R[HWD] for multi-element constants on big-endian targets.
	* gcc.target/aarch64/sve/slp_3.c: Likewise.
	* gcc.target/aarch64/sve/slp_4.c: Likewise.

Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>

From-SVN: r257288

The fallback way of handling a repeated 128-bit constant vector for SVE
is to force the 128 bits to the constant pool and use LD1RQ to load it.
Previously the code always used the byte variant of LD1RQ (LD1RQB),
with a preceding BSWAP for big-endian targets.  However, that BSWAP
doesn't handle all cases correctly.

The simplest fix seemed to be to use the LD1RQ appropriate for the
element size.

This helps to fix some of the sve/slp_*.c tests for aarch64_be,
although a later patch is needed as well.

2018-02-01  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	* config/aarch64/aarch64-sve.md (sve_ld1rq): Replace with...
	(*sve_ld1rq<Vesize>): ... this new pattern.  Handle all element sizes,
	not just bytes.
	* config/aarch64/aarch64.c (aarch64_expand_sve_widened_duplicate):
	Remove BSWAP handing for big-endian targets and use the form of
	LD1RQ appropariate for the mode.

gcc/testsuite/
	* gcc.target/aarch64/sve/slp_2.c: Expect LD1RQD rather than LD1RQB.
	* gcc.target/aarch64/sve/slp_3.c: Expect LD1RQW rather than LD1RQB.
	* gcc.target/aarch64/sve/slp_4.c: Expect LD1RQH rather than LD1RQB.

Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>

From-SVN: r257287