1. 04 Jun, 2015 6 commits
    • re PR target/66369 (gcc 4.8.3/5.1.0 miss optimisation with vpmovmskb) · e7f40208
      	PR target/66369
      	* config/i386/sse.md (<sse2_avx2>_pmovmsk): Merge from avx2_pmovmskb
      	and sse2_pmovmskb using VI1_AVX2 mode iterator.
      	(*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext): New insn pattern.
      	(*<sse2_avx2>_pmovmskb_zext): Ditto.
      
      From-SVN: r224120
      Uros Bizjak committed
    • [patch, testsuite, ARM] don't clobber dg-do-what-default in advsimd-intrinsics.exp · 676d1384
      gcc/testsuite/
      
      	* gcc.target/aarch64/advsimd-intrinsics/advsimd-intrinsics.exp:
      	Move set of dg-do-what-default after early return.
      
      From-SVN: r224119
      Sandra Loosemore committed
    • Remove TARGET_RELAXED_ORDERING and optimize for weak memory models. · e93ca5ca
      
      This patch removes the special casing for targets with relaxed
      memory ordering and handles guard accesses with equivalent
      atomic load acquire operations. In this process we change the
      algorithm to load the guard variable with an atomic load that
      has ACQUIRE semantics.
      
      This then means that on targets which have weak memory models, the
      fast path is inlined and can directly use a load-acquire instruction
      where available (and yay! one more hook gone).
      
      2015-06-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
      
      	PR c++/66192
      	PR target/66200
      	* doc/tm.texi: Regenerate.
      	* doc/tm.texi.in (TARGET_RELAXED_ORDERING): Delete.
      	* target.def (TARGET_RELAXED_ORDERING): Likewise.
      	* config/alpha/alpha.c (TARGET_RELAXED_ORDERING): Likewise.
      	* config/ia64/ia64.c (TARGET_RELAXED_ORDERING): Likewise.
      	* config/rs6000/rs6000.c (TARGET_RELAXED_ORDERING): Likewise.
      	* config/sparc/linux.h (SPARC_RELAXED_ORDERING): Likewise.
      	* config/sparc/linux64.h (SPARC_RELAXED_ORDERING): Likewise.
      	* config/sparc/sparc.c (TARGET_RELAXED_ORDERING): Likewise.
      	* config/sparc/sparc.h (SPARC_RELAXED_ORDERING): Likewise.
      	* system.h (TARGET_RELAXED_ORDERING): Poison.
      
      2015-06-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
      
      	PR c++/66192
      	PR target/66200
      	* cp-tree.h (get_guard_cond): Adjust declaration
      	* decl.c (expand_static_init): Use atomic load acquire
      	and adjust call to get_guard_cond.
      	* decl2.c (build_atomic_load_byte): New function.
      	(get_guard_cond): Handle thread_safety.
      	(one_static_initialization_or_destruction): Adjust call to
      	get_guard_cond.
      
      From-SVN: r224118
      Ramana Radhakrishnan committed
    • [AArch64] Always register fma_steering pass but gate it on the target option instead · e2fc7193
      	* config/aarch64/aarch64.c (aarch64_override_options): Unconditionally
      	register fma steering pass.
      	* config/aarch64/cortex-a57-fma-steering.c (gate): Add gating on
      	AARCH64_TUNE_FMA_STEERING.
      
      From-SVN: r224116
      Kyrylo Tkachov committed
    • re PR c/66341 (Some casts wrongly produce a lvalue) · 9482b620
      	PR c/66341
      	* c-typeck.c (build_c_cast): Wrap VALUE into NON_LVALUE_EXPR if
      	it is a lvalue.
      
      	* gcc.dg/lvalue-8.c: New test.
      
      From-SVN: r224115
      Marek Polacek committed
    • Daily bump. · 0b98bb4e
      From-SVN: r224112
      GCC Administrator committed
  2. 03 Jun, 2015 32 commits
  3. 02 Jun, 2015 2 commits