PR libfortran/93234
	* io/unit.c (set_internal_unit): Set round and sign flags
	correctly.

	* gfortran.dg/inquire_pre.f90: New test.

PR analyzer/93290 reports an ICE on calls to isnan().
The root cause is that an UNORDERED_EXPR is passed
to region_model::eval_condition_without_cm, and there's
a stray gcc_unreachable () in the case where we're comparing
an svalue against itself.

I attempted a more involved patch that properly handled NaN in general
but it seems I've baked the assumption of reflexivity too deeply into
the constraint_manager code.

For now, this patch avoids the ICE and documents the limitation.

gcc/analyzer/ChangeLog:
	PR analyzer/93290
	* region-model.cc (region_model::eval_condition_without_cm): Avoid
	gcc_unreachable for unexpected operations for the case where
	we're comparing an svalue against itself.

gcc/ChangeLog
	* doc/analyzer.texi (Limitations): Add note about NaN.

gcc/testsuite/ChangeLog:
	PR analyzer/93290
	* gcc.dg/analyzer/pr93290.c: New test.

	PR libfortran/90374
	* io/format.c (parse_format_list): Zero width not allowed with
	FMT_D.
	* io/write_float.def (build_float_string): Include range of
	higher exponent values that require wider width.

	PR c++/92542
	* g++.dg/pr92542.C: New.

	PR c++/92542
	* g++.dg/pr92542.C: New.

[GCC/ARM, 2/2] Add support for ASRL(imm), LSLL(imm) and LSRL(imm) instructions for Armv8.1-M Mainline

This patch is adding the following instructions:

ASRL (imm)
LSLL (imm)
LSRL (imm)

*** gcc/ChangeLog ***

2020-01-17  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
	    Sudakshina Das  <sudi.das@arm.com>

	* config/arm/arm.md (ashldi3): Generate thumb2_lsll for both reg
	and valid immediate.
	(ashrdi3): Generate thumb2_asrl for both reg and valid immediate.
	(lshrdi3): Generate thumb2_lsrl for valid immediates.
	* config/arm/constraints.md (Pg): New.
	* config/arm/predicates.md (long_shift_imm): New.
	(arm_reg_or_long_shift_imm): Likewise.
	* config/arm/thumb2.md (thumb2_asrl): New immediate alternative.
	(thumb2_lsll): Likewise.
	(thumb2_lsrl): New.

*** gcc/testsuite/ChangeLog ***

2020-01-17  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
	    Sudakshina Das  <sudi.das@arm.com>

	* gcc.target/arm/armv8_1m-shift-imm_1.c: New test.

This patch is adding the following instructions:

ASRL (reg)
LSLL (reg)

*** gcc/ChangeLog ***

2020-01-17  Mihail-Calin Ionescu <mihail.ionescu@arm.com>
	    Sudakshina Das  <sudi.das@arm.com>

	* config/arm/arm.md (ashldi3): Generate thumb2_lsll for TARGET_HAVE_MVE.
	(ashrdi3): Generate thumb2_asrl for TARGET_HAVE_MVE.
	* config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd
	register pairs for doubleword quantities for ARMv8.1M-Mainline.
	* config/arm/thumb2.md (thumb2_asrl): New.
	(thumb2_lsll): Likewise.

2020-01-17  Mihail-Calin Ionescu <mihail.ionescu@arm.com>
	    Sudakshina Das  <sudi.das@arm.com>

	* gcc.target/arm/armv8_1m-shift-reg_1.c: New test.

2020-01-17  Jakub Jelinek  <jakub@redhat.com>

	* config/arm/arm.c (cmse_nonsecure_call_inline_register_clear): Remove
	unused variable.

2020-01-17  Andrew Stubbs  <ams@codesourcery.com>

	libgomp/
	* config/accel/openacc.f90 (openacc_kinds): Rename acc_device_gcn to
	acc_device_radeon.
	(openacc): Likewise.
	* openacc.f90 (openacc_kinds): Likewise.
	(openacc): Likewise.
	* openacc.h (acc_device_t): Likewise.
	* openacc_lib.h: Likewise.
	* testsuite/lib/libgomp.exp
	(check_effective_target_openacc_amdgcn_accel_present): Likewise.
	* testsuite/libgomp.oacc-c-c++-common/acc_prof-init-1.c
	(cb_compute_construct_end): Likewise.
	* testsuite/libgomp.oacc-c-c++-common/acc_prof-kernels-1.c
	(cb_enqueue_launch_start): Likewise.
	* testsuite/libgomp.oacc-c-c++-common/acc_prof-parallel-1.c
	(cb_enter_data_end): Likewise.
	(cb_exit_data_start): Likewise.
	(cb_exit_data_end): Likewise.
	(cb_compute_construct_end): Likewise.
	(cb_enqueue_launch_start): Likewise.
	(cb_enqueue_launch_end): Likewise.
	* testsuite/libgomp.oacc-c-c++-common/asyncwait-nop-1.c
	(main): Likewise.

In a freestanding library we don't install the <pstl/pstl_config.h>
header, so don't try to include it unless it exists.

Explicitly declare aligned alloc functions for freestanding, because
<cstdlib> doesn't declare them.

	PR libstdc++/92376
	* include/bits/c++config: Only do PSTL config when the header is
	present, to fix freestanding.
	* libsupc++/new_opa.cc [!_GLIBCXX_HOSTED]: Declare allocation
	functions if they were detected by configure.

Make gdb shorthands such as 'pr' accept an argument, in addition to
implictly taking register '$' as the thing to examine.

The 'eval ...' one-liners are used to workaround GDB bug #22466.

	* gdbinit.in (help-gcc-hooks): New command.
	(pp, pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, ptc, pdn, ptn, pdd, prc,
	pi, pbm, pel, trt): Take $arg0 instead of $ if supplied. Update
	documentation.

Had mistakenly used a target macro that was not defined and not the
relevant one instead of the macro that should be used.

TARGET_ARMV8_6 is not defined, and also not the macro we want to check.
Instead check TARGET_F64MM.

gcc/ChangeLog:

2020-01-17  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use
	the correct target macro.

	PR testsuite/93227
	* g++.dg/cpp0x/std-layout1.C: Use -Wno-deprecated-declarations for
	C++20, due to std::is_pod being deprecated.

We take no action to ensure the SVE vector size is large enough.  It is
left to the user to check that before compiling this intrinsic or before
running such a program on a machine.

The main difference between ld1ro and ld1rq is in the allowed offsets,
the implementation difference is that ld1ro is implemented using integer
modes since there are no pre-existing vector modes of the relevant size.
Adding new vector modes simply for this intrinsic seems to make the code
less tidy.

Specifications can be found under the "Arm C Language Extensions for
Scalable Vector Extension" title at
https://developer.arm.com/architectures/system-architectures/software-standards/acle

gcc/ChangeLog:

2020-01-17  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/aarch64/aarch64-protos.h
	(aarch64_sve_ld1ro_operand_p): New.
	* config/aarch64/aarch64-sve-builtins-base.cc
	(class load_replicate): New.
	(class svld1ro_impl): New.
	(class svld1rq_impl): Change to inherit from load_replicate.
	(svld1ro): New sve intrinsic function base.
	* config/aarch64/aarch64-sve-builtins-base.def (svld1ro):
	New DEF_SVE_FUNCTION.
	* config/aarch64/aarch64-sve-builtins-base.h
	(svld1ro): New decl.
	* config/aarch64/aarch64-sve-builtins.cc
	(function_expander::add_mem_operand): Modify assert to allow
	OImode.
	* config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): New
	pattern.
	* config/aarch64/aarch64.c
	(aarch64_sve_ld1rq_operand_p): Implement in terms of ...
	(aarch64_sve_ld1rq_ld1ro_operand_p): This.
	(aarch64_sve_ld1ro_operand_p): New.
	* config/aarch64/aarch64.md (UNSPEC_LD1RO): New unspec.
	* config/aarch64/constraints.md (UOb,UOh,UOw,UOd): New.
	* config/aarch64/predicates.md
	(aarch64_sve_ld1ro_operand_{b,h,w,d}): New.

gcc/testsuite/ChangeLog:

2020-01-17  Matthew Malcomson  <matthew.malcomson@arm.com>

	* gcc.target/aarch64/sve/acle/asm/ld1ro_f16.c: New test.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_f32.c: New test.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_f64.c: New test.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_s16.c: New test.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_s32.c: New test.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_s64.c: New test.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_s8.c: New test.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_u16.c: New test.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_u32.c: New test.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_u64.c: New test.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_u8.c: New test.

This patch is necessary for sve-ld1ro intrinsic I posted in
https://gcc.gnu.org/ml/gcc-patches/2020-01/msg00466.html .

I had mistakenly thought this option was already enabled upstream.

This provides the option +f64mm, that turns on the 64 bit floating point
matrix multiply extension.  This extension is only available for
AArch64.  Turning on this extension also turns on the SVE extension.

This extension is optional and only available at Armv8.2-A and onward.

We also add the ACLE defined macro for this extension.

gcc/ChangeLog:

2020-01-17  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/aarch64/aarch64-c.c (_ARM_FEATURE_MATMUL_FLOAT64):
	Introduce this ACLE specified predefined macro.
	* config/aarch64/aarch64-option-extensions.def (f64mm): New.
	(fp): Disabling this disables f64mm.
	(simd): Disabling this disables f64mm.
	(fp16): Disabling this disables f64mm.
	(sve): Disabling this disables f64mm.
	* config/aarch64/aarch64.h (AARCH64_FL_F64MM): New.
	(AARCH64_ISA_F64MM): New.
	(TARGET_F64MM): New.
	* doc/invoke.texi (f64mm): Document new option.

gcc/testsuite/ChangeLog:

2020-01-17  Matthew Malcomson  <matthew.malcomson@arm.com>

	* gcc.target/aarch64/pragma_cpp_predefs_2.c: Check for f64mm
	predef.

Enable the most basic form of compare-branch fusion since various CPUs
support it. This has no measurable effect on cores which don't support
branch fusion, but increases fusion opportunities on cores which do.

gcc/
	* config/aarch64/aarch64.c (generic_tunings): Add branch fusion.
	(neoversen1_tunings): Likewise.

This was failing because uses_template_parms didn't recognize LAMBDA_EXPR as
a kind of expression.  Instead of trying to enumerate all the different
varieties of expression and then aborting if what's left isn't
error_mark_node, let's handle error_mark_node and then assume anything else
is an expression.

	* pt.c (uses_template_parms): Don't try to enumerate all the
	expression cases.

As the following testcase shows, when deprecated attribute is on a template,
we'd never print the message if any, because the attribute is not
present on the TEMPLATE_DECL with which warn_deprecated_use is called,
but on its DECL_TEMPLATE_RESULT or its type.

2020-01-17  Jakub Jelinek  <jakub@redhat.com>

	PR c++/93228
	* parser.c (cp_parser_template_name): Look up deprecated attribute
	in DECL_TEMPLATE_RESULT or its type's attributes.

	* g++.dg/cpp1y/attr-deprecated-3.C: New test.

the preprocessor evaluator has a skip_eval counter, but we weren't
checking it after parsing has_include(foo), but before looking for
foo.  Resulting in unnecessary io for 'FALSE_COND && has_include <foo>'

	PR preprocessor/93306
	* expr.c (parse_has_include): Refactor.  Check skip_eval before
	looking.

Various 32-bit targets show failures in gcc.dg/analyzer/data-model-1.c
with tests of the form:
  __analyzer_eval (q[-2].x == 107024); /* { dg-warning "TRUE" } */
  __analyzer_eval (q[-2].y == 107025); /* { dg-warning "TRUE" } */
where they emit UNKNOWN instead.

The root cause is that gimple has a byte-based twos-complement offset
of -16 expressed like this:
  _55 = q_92 + 4294967280;  (32-bit)
or:
  _55 = q_92 + 18446744073709551600; (64-bit)

Within region_model::convert_byte_offset_to_array_index that unsigned
offset was being divided by the element size to get an offset within
an array.

This happened to work on 64-bit target and host, but not elsewhere;
the offset needs to be converted to a signed type before the division
is meaningful.

This patch does so, fixing the failures.

gcc/analyzer/ChangeLog:
	PR analyzer/93281
	* region-model.cc
	(region_model::convert_byte_offset_to_array_index): Convert to
	ssizetype before dividing by byte_size.  Use fold_binary rather
	than fold_build2 to avoid needlessly constructing a tree for the
	non-const case.

The separate shrinkwrapping pass may insert stores in the middle
of atomics loops which can cause issues on some implementations.
Avoid this by delaying splitting atomics patterns until after
prolog/epilog generation.

gcc/
	PR target/92692
	* config/aarch64/aarch64.c (aarch64_split_compare_and_swap)
	Add assert to ensure prolog has been emitted.
	(aarch64_split_atomic_op): Likewise.
	* config/aarch64/atomics.md (aarch64_compare_and_swap<mode>)
	Use epilogue_completed rather than reload_completed.
	(aarch64_atomic_exchange<mode>): Likewise.
	(aarch64_atomic_<atomic_optab><mode>): Likewise.
	(atomic_nand<mode>): Likewise.
	(aarch64_atomic_fetch_<atomic_optab><mode>): Likewise.
	(atomic_fetch_nand<mode>): Likewise.
	(aarch64_atomic_<atomic_optab>_fetch<mode>): Likewise.
	(atomic_nand_fetch<mode>): Likewise.

AIUI, the main purpose of REVERSE_CONDITION is to take advantage of
any integer vs. FP information encoded in the CC mode, particularly
when handling LT, LE, GE and GT.  For integer comparisons we can
safely map LT->GE, LE->GT, GE->LT and GT->LE, but for float comparisons
this would usually be invalid without -ffinite-math-only.

The aarch64 definition of REVERSE_CONDITION used
reverse_condition_maybe_unordered for FP comparisons, which had the
effect of converting an unordered-signalling LT, LE, GE or GT into a
quiet UNGE, UNGT, UNLT or UNLE.  And it would do the same in reverse:
convert a quiet UN* into an unordered-signalling comparison.

This would be safe in practice (although a little misleading) if we
always used a compare:CCFP or compare:CCFPE to do the comparison and
then used (gt (reg:CCFP/CCFPE CC_REGNUM) (const_int 0)) etc. to test
the result.  In that case any signal is raised by the compare and the
choice of quiet vs. signalling relations doesn't matter when testing
the result.  The problem is that we also want to use GT directly on
float registers, where any signal is raised by the comparison operation
itself and so must follow the normal rtl rules (GT signalling,
UNLE quiet).

I think the safest fix is to make REVERSIBLE_CC_MODE return false
for FP comparisons.  We can then use the default REVERSE_CONDITION
for integer comparisons and the usual conservatively-correct
reversed_comparison_code_parts behaviour for FP comparisons.
Unfortunately reversed_comparison_code_parts doesn't yet handle
-ffinite-math-only, but that's probably GCC 11 material.

A downside is that:

    int f (float x, float y) { return !(x < y); }

now generates:

        fcmpe   s0, s1
        cset    w0, mi
        eor     w0, w0, 1
        ret

without -ffinite-math-only.  Maybe for GCC 11 we should define rtx
codes for all IEEE comparisons, so that we don't have this kind of
representational gap.

Changing REVERSE_CONDITION itself is pretty easy.  However, the macro
was also used in the ccmp handling, which relied on being able to
reverse all comparisons.  The patch adds new reversed patterns for
cases in which the original condition needs to be kept.

The test is based on gcc.dg/torture/pr91323.c.  It might well fail
on other targets that have similar bugs; please XFAIL as appropriate
if you don't want to fix the target for GCC 10.

2020-01-17  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64.h (REVERSIBLE_CC_MODE): Return false
	for FP modes.
	(REVERSE_CONDITION): Delete.
	* config/aarch64/iterators.md (CC_ONLY): New mode iterator.
	(CCFP_CCFPE): Likewise.
	(e): New mode attribute.
	* config/aarch64/aarch64.md (ccmp<GPI:mode>): Rename to...
	(@ccmp<CC_ONLY:mode><GPI:mode>): ...this, using CC_ONLY instead of CC.
	(fccmp<GPF:mode>, fccmpe<GPF:mode>): Merge into...
	(@ccmp<CCFP_CCFPE:mode><GPF:mode>): ...this combined pattern.
	(@ccmp<CC_ONLY:mode><GPI:mode>_rev): New pattern.
	(@ccmp<CCFP_CCFPE:mode><GPF:mode>_rev): Likewise.
	* config/aarch64/aarch64.c (aarch64_gen_compare_reg): Update
	name of generator from gen_ccmpdi to gen_ccmpccdi.
	(aarch64_gen_ccmp_next): Use code_for_ccmp.  If we want to reverse
	the previous comparison but aren't able to, use the new ccmp_rev
	patterns instead.

If a TARGET_EXPR has poly-int size, the gimplifier would treat it
like a VLA and use gimplify_vla_decl.  gimplify_vla_decl in turn
would use an alloca and expect all references to be gimplified
via the DECL_VALUE_EXPR.  This caused confusion later in
gimplify_var_or_parm_decl_1 when we (correctly) had direct rather
than indirect references.

For completeness, the patch also fixes similar tests in the RETURN_EXPR
handling and OpenMP depend clauses.

2020-01-17  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* gimplify.c (gimplify_return_expr): Use poly_int_tree_p rather
	than testing directly for INTEGER_CST.
	(gimplify_target_expr, gimplify_omp_depend): Likewise.

gcc/testsuite/
	* g++.target/aarch64/sve/acle/general-c++/gimplify_1.C: New test.

The use of -fno-automatic should not affect the save attribute of a
recursive procedure. The first test case checks unsaved variables
and the second checks saved variables.

The following testcase ICEs on powerpc64le-linux.  The problem is that
get_vectype_for_scalar_type returns NULL, and while most places in
tree-vect-stmts.c handle that case, this spot doesn't and punts only
if it is non-NULL, but with different number of elts than expected.

2020-01-17  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/93292
	* tree-vect-stmts.c (vectorizable_comparison): Punt also if
	get_vectype_for_scalar_type returns NULL.

	* g++.dg/opt/pr93292.C: New test.

2020-01-17  Jakub Jelinek  <jakub@redhat.com>

	PR testsuite/93294
	* lib/c-compat.exp (compat-use-alt-compiler): Handle
	-fdiagnostics-urls=never similarly to -fdiagnostics-color=never.
	(compat_setup_dfp): Likewise.

Really old git versions (like 1.6.0) require
"git log --pretty=tformat:%p:%t:%H"
or else we see:

Updating GIT tree
Current branch master is up to date.
fatal: invalid --pretty format: %p:%t:%H
Adjusting file timestamps
Touching gcc/config.in...
Touching gcc/config/arm/arm-tune.md...

...and an empty revision in LAST_UPDATED and gcc/REVISION.
In its absence, for newer git versions, "tformat" is the default
qualifier, documented as such default for at least git-2.11.0.

Here we had been recursing in tsubst_copy_and_build if type2 was a TREE_LIST
because that function knew how to deal with pack expansions, and tsubst
didn't.  But tsubst_copy_and_build expects to be dealing with expressions,
so we crash when trying to convert_from_reference a type.

	* pt.c (tsubst) [TREE_LIST]: Handle pack expansion.
	(tsubst_copy_and_build) [TRAIT_EXPR]: Always use tsubst for type2.

	* params.opt (-param=max-predicted-iterations): Increase range from 0.
	* predict.c (estimate_loops): Add 1 to param_max_predicted_iterations.

This patch fixes ICE on invalid code, specifically files that have
conflict-marker-like signs before EOF.

	PR c/92833
gcc/c/
	* c-parser.c (c_parser_consume_token): Fix peeked token stack pop
	to support 4 available tokens.

gcc/testsuite/
	* c-c++-common/pr92833-1.c, c-c++-common/pr92833-2.c,
	c-c++-common/pr92833-3.c, c-c++-common/pr92833-4.c: New tests.

While analyzing code size regression in SPEC2k GCC binary I noticed that we
perform some inline decisions because we think that number of executions are
very high.
In particular there was inline decision inlining gen_rtx_fmt_ee to find_reloads
believing that it is called 4 billion times.  This turned out to be cummulation
of roundoff errors in propagate_freq which was bit mechanically updated from
original sreals to C++ sreals and later to new probabilities.

This led us to estimate that a loopback edge is reached with probability 2.3
which was capped to 1-1/10000 and since this happened in nested loop it quickly
escalated to large values.

Originally capping to REG_BR_PROB_BASE avoided such problems but now we have
much higher range.

This patch avoids going from probabilites to REG_BR_PROB_BASE so precision is
kept.  In addition it makes the propagation to not estimate more than
param-max-predicted-loop-iterations.  The first change makes the cap to not
be triggered on the gcc build, but it is still better to be safe than sorry.

	* ipa-fnsummary.c (estimate_calls_size_and_time): Fix formating of
	dump.
	* params.opt: (max-predicted-iterations): Set bounds.
	* predict.c (real_almost_one, real_br_prob_base,
	real_inv_br_prob_base, real_one_half, real_bb_freq_max): Remove.
	(propagate_freq): Add max_cyclic_prob parameter; cap cyclic
	probabilities; do not truncate to reg_br_prob_bases.
	(estimate_loops_at_level): Pass max_cyclic_prob.
	(estimate_loops): Compute max_cyclic_prob.
	(estimate_bb_frequencies): Do not initialize real_*; update calculation
	of back edge prob.
	* profile-count.c (profile_probability::to_sreal): New.
	* profile-count.h (class sreal): Move up in file.
	(profile_probability::to_sreal): Declare.

I recently added an assert to cp-gimplify to catch any
TARGET_EXPR_DIRECT_INIT_P being expanded without a target object, and this
testcase found one.  We started out with a TARGET_EXPR around the
CONSTRUCTOR, which would normally mean that the member initializer would be
used to directly initialize the appropriate member of whatever object the
TARGET_EXPR ends up initializing.  But then gimplify_modify_expr_rhs
stripped the TARGET_EXPR in order to assign directly from the elements of
the CONSTRUCTOR, leaving no object for the TARGET_EXPR_DIRECT_INIT_P to
initialize.  I considered setting CONSTRUCTOR_PLACEHOLDER_BOUNDARY in that
case, which implies TARGET_EXPR_NO_ELIDE, but decided that there's no
particular reason the A initializer needs to initialize a member of a B
rather than a distinct A object, so let's only set TARGET_EXPR_DIRECT_INIT_P
when we're using the DMI in a constructor.

	* init.c (get_nsdmi): Set TARGET_EXPR_DIRECT_INIT_P here.
	* typeck2.c (digest_nsdmi_init): Not here.

	* lto-partition.c (lto_balanced_map): Remember
	best_noreorder_pos and then restore to it
	when we revert.

This removes support for EOL versions of NetBSD and syncs the
definitions with patches from NetBSD upstream.

The only change here that isn't from upstream is to use _CTYPE_BL for
the isblank class, which is correct but wasn't previously done either in
FSF GCC or the NetBSD packages.

2020-01-16  Kai-Uwe Eckhardt  <kuehro@gmx.de>
	    Matthew Bauer  <mjbauer95@gmail.com>
	    Jonathan Wakely  <jwakely@redhat.com>

	PR bootstrap/64271 (partial)
	* config/os/bsd/netbsd/ctype_base.h (ctype_base::mask): Change type
	to unsigned short.
	(ctype_base::alpha, ctype_base::digit, ctype_base::xdigit)
	(ctype_base::print, ctype_base::graph, ctype_base::alnum): Sync
	definitions with NetBSD upstream.
	(ctype_base::blank): Use _CTYPE_BL.
	* config/os/bsd/netbsd/ctype_configure_char.cc (_C_ctype_): Remove
	Declaration.
	(ctype<char>::classic_table): Use _C_ctype_tab_ instead of _C_ctype_.
	(ctype<char>::do_toupper, ctype<char>::do_tolower): Cast char
	parameters to unsigned char.
	* config/os/bsd/netbsd/ctype_inline.h (ctype<char>::is): Likewise.

gcc/ChangeLog:

2020-01-16  Stam Markianos-Wright  <stam.markianos-wright@arm.com>

	* config/arm/arm.c
	(arm_invalid_conversion): New function for target hook.
	(arm_invalid_unary_op): New function for target hook.
	(arm_invalid_binary_op): New function for target hook.

gcc/testsuite/ChangeLog:

2020-01-16  Stam Markianos-Wright  <stam.markianos-wright@arm.com>

	* g++.target/arm/bfloat_cpp_typecheck.C: New test.
	* gcc.target/arm/bfloat16_scalar_typecheck.c: New test.
	* gcc.target/arm/bfloat16_vector_typecheck_1.c: New test.
	* gcc.target/arm/bfloat16_vector_typecheck_2.c: New test.