2016-11-17  Toma Tabacu  <toma.tabacu@imgtec.com>

	* gcc.target/mips/branch-cost-1.c (dg-options): Use (HAS_MOVN)
	instead of isa>=4, in order to downgrade to R5.

From-SVN: r242574

	* call.c (build_over_call): Don't set CALL_FROM_THUNK_P here.
	(build_call_a): Set it here, and don't insert EMPTY_CLASS_EXPR.
	(convert_like_real) [ck_rvalue]: Also pass non-addressable
	types along directly.

From-SVN: r242573

In the case where we access a single bit from a value and use this in a
EQ/NE comparison, GCC will convert this into a sign-extend and GE/LT
comparison.

Normally this would be fine, however, if the value is in CMEM memory,
then we don't have a sign-extending load available (using the special
short CMEM load instructions), and instead we end up using a long form
load with LIMM, which is less efficient.

This peephole optimisation looks for the sign-extend followed by GE/LT
pattern and converts this back into a load and EQ/NE comparison.

gcc/ChangeLog:

	* config/arc/arc.md (cmem bit/sign-extend peephole2): New peephole
	to make better use of cmem loads in the case where a single bit is
	being accessed.
	* config/arc/predicates.md (ge_lt_comparison_operator): New
	predicate.

gcc/testsuite/ChangeLog:

	* gcc.target/arc/cmem-bit-1.c: New file.
	* gcc.target/arc/cmem-bit-2.c: New file.
	* gcc.target/arc/cmem-bit-3.c: New file.
	* gcc.target/arc/cmem-bit-4.c: New file.

From-SVN: r242572

gcc/

2016-11-17  Andrew Senkevich <andrew.senkevich@intel.com>

	* config/i386/i386.c (processor_features): Add F_AVX5124VNNIW,
	F_AVX5124FMAPS.
	(isa_names_table): Handle new features.

gcc/testsuite/

2016-11-17  Andrew Senkevich <andrew.senkevich@intel.com>

	* gcc.target/i386/builtin_target.c: Handle new "avx5124vnniw",
	"avx5124fmaps".
	* gcc.target/i386/funcspec-56.inc: Test new attributes.

libgcc/

2016-11-17  Andrew Senkevich <andrew.senkevich@intel.com>

	* config/i386/cpuinfo.c (processor_features): Add
	FEATURE_AVX5124VNNIW, FEATURE_AVX5124FMAPS.

From-SVN: r242570

This requires additional patch for register allocator from Vladimir
Makarov.

gcc/

2016-11-17  Kirill Yukhin  <kirill.yukhin@gmail.com>
	    Andrew Senkevich <andrew.senkevich@intel.com>

	* common/config/i386/i386-common.c
	(OPTION_MASK_ISA_AVX5124FMAPS_SET,
	OPTION_MASK_ISA_AVX5124FMAPS_UNSET,
	OPTION_MASK_ISA_AVX5124VNNIW_SET,
	OPTION_MASK_ISA_AVX5124VNNIW_UNSET): New.
	(ix86_handle_option): Handle OPT_mavx5124fmaps,
	OPT_mavx5124vnniw.
	* config.gcc: Add avx5124fmapsintrin.h, avx5124vnniwintrin.h.
	* config/i386/avx5124fmapsintrin.h: New file.
	* config/i386/avx5124vnniwintrin.h: Ditto.
	* config/i386/constraints.md (h): New constraint.
	* config/i386/cpuid.h: (bit_AVX5124VNNIW,
	bit_AVX5124FMAPS): New.
	* config/i386/driver-i386.c (host_detect_local_cpu):
	Detect avx5124fmaps, avx5124vnniw.
	* config/i386/i386-builtin-types.def: Add types
	V16SF_FTYPE_V16SF_V16SF_V16SF_V16SF_V16SF_PCV4SF_V16SF_UHI,
	V16SF_FTYPE_V16SF_V16SF_V16SF_V16SF_V16SF_PCV4SF,
	V4SF_FTYPE_V4SF_V4SF_V4SF_V4SF_V4SF_PCV4SF,
	V4SF_FTYPE_V4SF_V4SF_V4SF_V4SF_V4SF_PCV4SF_V4SF_UQI,
	V16SI_FTYPE_V16SI_V16SI_V16SI_V16SI_V16SI_PCV4SI,
	V16SI_FTYPE_V16SI_V16SI_V16SI_V16SI_V16SI_PCV4SI_V16SI_UHI.
	* config/i386/i386-builtin.def (__builtin_ia32_4fmaddps_mask,
	__builtin_ia32_4fmaddps, __builtin_ia32_4fmaddss,
	__builtin_ia32_4fmaddss_mask, __builtin_ia32_4fnmaddps_mask,
	__builtin_ia32_4fnmaddps, __builtin_ia32_4fnmaddss,
	__builtin_ia32_4fnmaddss_mask, __builtin_ia32_vp4dpwssd,
	__builtin_ia32_vp4dpwssd_mask, __builtin_ia32_vp4dpwssds,
	__builtin_ia32_vp4dpwssds_mask): New.
	* config/i386/i386-c.c (ix86_target_macros_internal):
	Define __AVX5124FMAPS__, __AVX5124VNNIW__.
	* config/i386/i386-modes.def: Fixed comment typos, added new
	modes (VECTOR_MODES (FLOAT, 256), VECTOR_MODE (INT, SI, 64)).
	* config/i386/i386.c (ix86_target_string): Add -mavx5124fmaps,
	-mavx5124vnniw.
	(PTA_AVX5124FMAPS, PTA_AVX5124VNNIW): Define.
	(ix86_option_override_internal): Handle new options.
	(ix86_valid_target_attribute_inner_p): Add avx5124fmaps,
	avx5124vnniw.
	(ix86_expand_builtin): Handle new builtins.
	(ix86_additional_allocno_class_p): New.
	* config/i386/i386.h (TARGET_AVX5124FMAPS,
	TARGET_AVX5124FMAPS_P,
	TARGET_AVX5124VNNIW,
	TARGET_AVX5124VNNIW_P): Define.
	(reg_class): Add MOD4_SSE_REGS.
	(MOD4_SSE_REG_P, MOD4_SSE_REGNO_P): New.
	* config/i386/i386.opt: Add mavx5124fmaps, mavx5124vnniw.
	* config/i386/immintrin.h: Include avx5124fmapsintrin.h,
	avx5124vnniwintrin.h.
	* config/i386/sse.md (unspec): Add UNSPEC_VP4FMADD,
	UNSPEC_VP4FNMADD,
	UNSPEC_VP4DPWSSD, UNSPEC_VP4DPWSSDS.
	(define_mode_iterator IMOD4): New.
	(define_mode_attr imod4_narrow): Ditto.
	(define_insn "mov<mode>"): Ditto.
	(define_insn "avx5124fmaddps_4fmaddps"): Ditto.
	(define_insn "avx5124fmaddps_4fmaddps_mask"): Ditto.
	(define_insn "avx5124fmaddps_4fmaddps_maskz"): Ditto.
	(define_insn "avx5124fmaddps_4fmaddss"): Ditto.
	(define_insn "avx5124fmaddps_4fmaddss_mask"): Ditto.
	(define_insn "avx5124fmaddps_4fmaddss_maskz"): Ditto.
	(define_insn "avx5124fmaddps_4fnmaddps"): Ditto.
	(define_insn "avx5124fmaddps_4fnmaddps_mask"): Ditto.
	(define_insn "avx5124fmaddps_4fnmaddps_maskz"): Ditto.
	(define_insn "avx5124fmaddps_4fnmaddss"): Ditto.
	(define_insn "avx5124fmaddps_4fnmaddss_mask"): Ditto.
	(define_insn "avx5124fmaddps_4fnmaddss_maskz"): Ditto.
	(define_insn "avx5124vnniw_vp4dpwssd"): Ditto.
	(define_insn "avx5124vnniw_vp4dpwssd_mask"): Ditto.
	(define_insn "avx5124vnniw_vp4dpwssd_maskz"): Ditto.
	(define_insn "avx5124vnniw_vp4dpwssds"): Ditto.
	(define_insn "avx5124vnniw_vp4dpwssds_mask"): Ditto.
	(define_insn "avx5124vnniw_vp4dpwssds_maskz"): Ditto.
	* init-regs.c (initialize_uninitialized_regs): Add emit_clobber call.
	* genmodes.c (mode_size_inline): Extend return type.
	* machmode.h (mode_size, mode_base_align): Extend type.

gcc/testsuite/

2016-11-17  Kirill Yukhin  <kirill.yukhin@gmail.com>
	    Andrew Senkevich <andrew.senkevich@intel.com>

	* gcc.target/i386/avx5124fmadd-v4fmaddps-1.c: New test.
	* gcc.target/i386/avx5124fmadd-v4fmaddps-2.c: Ditto.
	* gcc.target/i386/avx5124fmadd-v4fmaddss-1.c: Ditto.
	* gcc.target/i386/avx5124fmadd-v4fnmaddps-1.c: Ditto.
	* gcc.target/i386/avx5124fmadd-v4fnmaddps-2.c: Ditto.
	* gcc.target/i386/avx5124fmadd-v4fnmaddss-1.c: Ditto.
	* gcc.target/i386/avx5124fmaps-check.h: Ditto.
	* gcc.target/i386/avx5124vnniw-check.h: Ditto.
	* gcc.target/i386/avx5124vnniw-vp4dpwssd-1.c: Ditto.
	* gcc.target/i386/avx5124vnniw-vp4dpwssd-2.c: Ditto.
	* gcc.target/i386/avx5124vnniw-vp4dpwssds-1.c: Ditto.
	* gcc.target/i386/avx5124vnniw-vp4dpwssds-2.c: Ditto.
	* gcc.target/i386/avx512f-helper.h: Add avx5124fmaps-check.h,
	avx5124vnniw-check.h.
	* gcc.target/i386/i386.exp (check_effective_target_avx5124fmaps,
	check_effective_target_avx5124vnniw): New.
	* gcc.target/i386/m128-check.h (ESP_FLOAT, ESP_DOUBLE):
	Set under ifndef.
	* gcc.target/i386/sse-12.c: Add -mavx5124fmaps, -mavx5124vnniw.
	* gcc.target/i386/sse-13.c: Ditto.
	* g++.dg/other/i386-2.C: Ditto.
	* g++.dg/other/i386-3.C: Ditto.
	* gcc.target/i386/sse-22.c: Ditto.
	* gcc.target/i386/sse-23.c: Ditto.

From-SVN: r242569

re PR c++/55080 (-pedantic produces error: floating-point literal cannot appear in a constant-expression)

/cp
2016-11-17  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/55080
	* parser.c (cp_parser_non_integral_constant_expression): Issue a
	pedwarn instead of an error for case NIC_FLOAT.

/testsuite
2016-11-17  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/55080
	* g++.dg/parse/pr55080.C: New.

From-SVN: r242565

[gcc]
2016-11-17  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/78101
	* config/rs6000/predicates.md (fusion_addis_mem_combo_load): Add
	the appropriate checks for SFmode/DFmode load/stores in GPR
	registers.
	(fusion_addis_mem_combo_store): Likewise.
	* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Rename
	fusion_fpr_* to fusion_vsx_* and add in support for ISA 3.0 scalar
	d-form instructions for traditional Altivec registers.
	(emit_fusion_p9_load): Likewise.
	(emit_fusion_p9_store): Likewise.
	* config/rs6000/rs6000.md (p9 fusion store peephole2): Remove
	early clobber from scratch register.  Do not match if the register
	being stored is the scratch register.
	(fusion_vsx_<P:mode>_<FPR_FUSION:mode>_load): Rename fusion_fpr_*
	to fusion_vsx_* and add in support for ISA 3.0 scalar d-form
	instructions for traditional Altivec registers.
	(fusion_fpr_<P:mode>_<FPR_FUSION:mode>_load): Likewise.
	(fusion_vsx_<P:mode>_<FPR_FUSION:mode>_store): Likewise.
	(fusion_fpr_<P:mode>_<FPR_FUSION:mode>_store): Likewise.

[gcc/testsuite]
2016-11-17  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/78101
	* gcc.target/powerpc/fusion4.c: New test.

From-SVN: r242564

	* name-lookup.c (do_class_using_decl): Set CLASSTYPE_NON_AGGREGATE.

From-SVN: r242563

	* call.c (build_special_member_call): Handle CONSTRUCTOR.

From-SVN: r242562

	* parser.c (cp_parser_fold_expression): Check TREE_NO_WARNING.

From-SVN: r242561

2016-11-17  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    PR target/77933
    * config/arm/arm.c (thumb1_expand_prologue): Distinguish between lr
    being live in the function and lr needing to be saved.  Distinguish
    between already saved pushable registers and registers to push.
    Check for LR being an available pushable register.

    gcc/testsuite/
    PR target/77933
    * gcc.target/arm/pr77933-1.c: New test.
    * gcc.target/arm/pr77933-2.c: Likewise.

From-SVN: r242559

2016-11-17  Aaron Sawdey  <acsawdey@linux.vnet.ibm.com>

	* config/i386/i386.md (cmpstrnsi): New test to bail out if neither
	string input is a string constant.
	* builtins.c (expand_builtin_strncmp): Attempt expansion of strncmp
	via cmpstrnsi even if neither string is constant.

From-SVN: r242556

	PR middle-end/78201
	* varasm.c (default_use_anchors_for_symbol_p): Fix a comment typo.
	Don't test decl != NULL.  Don't look at DECL_SIZE, but DECL_SIZE_UNIT
	instead, return false if it is NULL, or doesn't fit into uhwi, or
	is larger or equal to targetm.max_anchor_offset.

	* g++.dg/opt/pr78201.C: New test.

From-SVN: r242555

	PR rtl-optimization/78355
	* doc/tm.texi.in (SLOW_UNALIGNED_ACCESS): Document that the macro only
	needs to deal with unaligned accesses.
	* doc/tm.texi: Regenerate.
	* lra-constraints.c (simplify_operand_subreg): Only invoke
	SLOW_UNALIGNED_ACCESS on innermode if the MEM is not aligned enough.

Co-Authored-By: Eric Botcazou <ebotcazou@adacore.com>

From-SVN: r242554

2016-11-17  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/testsuite/

	* gcc.dg/pr78333.c: Add empty implementations of
	__cyg_profile_func_enter() and __cyg_profile_func_exit() to avoid
	problems on non-glibc systems.

From-SVN: r242553

Whilst investigating PR preprocessor/78324 I noticed that the
substring location code currently doesn't handle raw strings
correctly, by not skipping the 'R', opening quote, delimiter
and opening parenthesis.

For example, an attempt to underline chars 4-7 with caret at 6 of
this raw string yields this erroneous output:
   __emit_string_literal_range (R"foo(0123456789)foo",
                                    ~~^~

With the patch, the correct range/caret is printed:

   __emit_string_literal_range (R"foo(0123456789)foo",
                                          ~~^~

gcc/ChangeLog:
	* input.c (selftest::test_lexer_string_locations_long_line): New
	function.
	(selftest::test_lexer_string_locations_raw_string_multiline): New
	function.
	(selftest::input_c_tests): Call the new functions, via
	for_each_line_table_case.

gcc/testsuite/ChangeLog:
	* gcc.dg/plugin/diagnostic-test-string-literals-1.c
	(test_raw_string_one_liner): New function.
	(test_raw_string_multiline): New function.

libcpp/ChangeLog:
	* charset.c (cpp_interpret_string_1): Skip locations from
	loc_reader when advancing 'p' when handling raw strings.

From-SVN: r242552

	* config/aarch64/aarch64.md (mov<mode>): Call
	aarch64_split_dimode_const_store on DImode constant stores.
	* config/aarch64/aarch64-protos.h (aarch64_split_dimode_const_store):
	New prototype.
	* config/aarch64/aarch64.c (aarch64_split_dimode_const_store): New
	function.

	* gcc.target/aarch64/store_repeating_constant_1.c: New test.
	* gcc.target/aarch64/store_repeating_constant_2.c: Likewise.

From-SVN: r242551

[gcc]

2016-11-17  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
            Richard Biener  <rguenther@suse.de>

	PR tree-optimization/77848
	* tree-if-conv.c (tree_if_conversion): Always version loops unless
	the user specified -ftree-loop-if-convert.

[gcc/testsuite]

2016-11-17  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
            Richard Biener  <rguenther@suse.de>

	PR tree-optimization/77848
	* gfortran.dg/vect/pr77848.f: New test.


Co-Authored-By: Richard Biener <rguenther@suse.de>

From-SVN: r242550

2016-11-17  Bernd Edlinger  <bernd.edlinger@hotmail.de>

        PR target/77308
        * config/arm/arm.md (*thumb2_ldrd, *thumb2_ldrd_base,
        *thumb2_ldrd_base_neg, *thumb2_strd, *thumb2_strd_base,
        *thumb2_strd_base_neg): Recognize insn regardless of
        current_tune->prefer_ldrd_strd.
        * config/arm/ldrdstrd.md: Enable all ldrd/strd peephole rules
        whenever possible.

testsuite:
2016-11-17  Bernd Edlinger  <bernd.edlinger@hotmail.de>

        PR target/77308
        * gcc.target/arm/pr53447-5.c: New test.
        * lib/target-supports.exp
        (check_effective_target_arm_prefer_ldrd_strd): Adjust.

From-SVN: r242549

gcc/
2016-11-17  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.c (arc_ccfsm_post_advance): Handle return
	instruction type.

From-SVN: r242548

libgcc/
2016-11-17  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/dp-hack.h (ARC_OPTFPE): Define.
	(__ARC_NORM__): Use instead ARC_OPTFPE.
	* config/arc/fp-hack.h: Likewise.
	* config/arc/lib1funcs.S (ARC_OPTFPE): Define.
	(__ARC_MPY__): Use it insetead of __ARC700__ and __HS__.

From-SVN: r242547

gcc/
2016-11-17  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc-arches.def: Add FPX quarkse instruction as valid
	for arcem.
	* config/arc/arc-c.def (__ARC_FPX_QUARK__): Define.
	* config/arc/arc-cpus.def (quarkse_em): Add.
	* config/arc/arc-options.def (FL_FPX_QUARK, FL_QUARK): Likewise.
	* config/arc/arc-opts.h (FPX_QK): Define.
	* config/arc/arc-tables.opt: Regenerate.
	* config/arc/arc.c (gen_compare_reg): Change.
	(arc_register_move_cost): Avoid Dy,Dx moves.
	* config/arc/arc.h (TARGET_HARD_FLOAT): Change.
	(TARGET_FPX_QUARK, TARGET_FP_ASSIST): Define.
	* config/arc/arc.md (divsf3, sqrtsf2, fix_truncsfsi2, floatsisf2):
	New expands.
	* config/arc/fpu.md (divsf3_fpu, sqrtsf2_fpu, floatsisf2_fpu)
	(fix_truncsfsi2_fpu): Rename.
	* config/arc/fpx.md (cmp_quark, cmpsf_quark_, cmpsf_quark_ord)
	(cmpsf_quark_uneq, cmpsf_quark_eq, divsf3_quark, sqrtsf2_quark)
	(fix_truncsfsi2_quark, floatsisf2_quark): New patterns.
	* config/arc/t-multilib: Regenerate.

From-SVN: r242546

gcc/testsuite
2016-11-17  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/abitest.S: New file.
	* gcc.target/arc/abitest.h: Likewise.
	* gcc.target/arc/va_args-1.c: Likewise.
	* gcc.target/arc/va_args-2.c: Likewise.
	* gcc.target/arc/va_args-3.c: Likewise.
	* gcc.target/arc/mcrc.c: Deleted.
	* gcc.target/arc/mdsp-packa.c: Likewise.
	* gcc.target/arc/mdvbf.c: Likewise.
	* gcc.target/arc/mmac-24.c: Likewise.
	* gcc.target/arc/mmac-d16.c: Likewise.
	* gcc.target/arc/mno-crc.c: Likewise.
	* gcc.target/arc/mno-dsp-packa.c: Likewise.
	* gcc.target/arc/mno-dvbf.c: Likewise.
	* gcc.target/arc/mno-mac-24.c: Likewise.
	* gcc.target/arc/mno-mac-d16.c: Likewise.
	* gcc.target/arc/mno-rtsc.c: Likewise.
	* gcc.target/arc/mno-xy.c: Likewise.
	* gcc.target/arc/mrtsc.c: Likewise.
	* gcc.target/arc/arc.exp (check_effective_target_arcem):
	New function.
	(check_effective_target_arc700): Likewise.
	(check_effective_target_arc6xx): Likewise.
	(check_effective_target_arcmpy): Likewise.
	(check_effective_target_archs): Likewise.
	(check_effective_target_clmcpu): Likewise.
	(check_effective_target_barrelshifter): Likewise.
	* gcc.target/arc/barrel-shifter-1.c: Changed.
	* gcc.target/arc/builtin_simd.c: Test only for ARC700
	cpus.
	* gcc.target/arc/cmem-1.c: Changed.
	* gcc.target/arc/cmem-2.c: Likewise.
	* gcc.target/arc/cmem-3.c: Likewise.
	* gcc.target/arc/cmem-4.c: Likewise.
	* gcc.target/arc/cmem-5.c: Likewise.
	* gcc.target/arc/cmem-6.c: Likewise.
	* gcc.target/arc/cmem-7.c: Likewise.
	* gcc.target/arc/interrupt-1.c: Test for RTIE as well.
	* gcc.target/arc/interrupt-2.c: Skip it for ARCv2 cores.
	* gcc.target/arc/interrupt-3.c: Match also ARCv2
	warnings.
	* gcc.target/arc/jump-around-jump.c: Update options.
	* gcc.target/arc/mARC601.c: Changed.
	* gcc.target/arc/mcpu-arc600.c: Changed.
	* gcc.target/arc/mcpu-arc601.c: Changed.
	* gcc.target/arc/mcpu-arc700.c: Changed.
	* gcc.target/arc/mdpfp.c: Skip for ARCv2 cores.
	* gcc.target/arc/movb-1.c: Changed.
	* gcc.target/arc/movb-2.c: Likewise.
	* gcc.target/arc/movb-3.c: Likewise.
	* gcc.target/arc/movb-4.c: Likewise.
	* gcc.target/arc/movb-5.c: Likewise.
	* gcc.target/arc/movb_cl-1.c: Likewise.
	* gcc.target/arc/movb_cl-2.c: Likewise.
	* gcc.target/arc/movbi_cl-1.c: Likewise.
	* gcc.target/arc/movh_cl-1.c: Likewise.
	* gcc.target/arc/mspfp.c: Skip for ARC HS cores.
	* gcc.target/arc/mul64.c: Enable it only for ARC600.
	* gcc.target/arc/mulsi3_highpart-1.c: Scan for ARCv2
	instructions.
	* gcc.target/arc/mulsi3_highpart-2.c: Skip it for ARCv1
	cores.
	* gcc.target/arc/no-dpfp-lrsr.c: Skip it for ARC HS.
	* gcc.target/arc/trsub.c: Only for ARC EM cores.
	* gcc.target/arc/builtin_simdarc.c: Changed.
	* gcc.target/arc/extzv-1.c: Likewise.
	* gcc.target/arc/insv-1.c: Likewise.
	* gcc.target/arc/insv-2.c: Likewise.
	* gcc.target/arc/mA6.c: Likewise.
	* gcc.target/arc/mA7.c: Likewise.
	* gcc.target/arc/mARC600.c: Likewise.
	* gcc.target/arc/mARC700.c: Likewise.
	* gcc.target/arc/mcpu-arc600.c: Likewise.
	* gcc.target/arc/mcpu-arc700.c: Likewise.
	* gcc.target/arc/movl-1.c: Likewise.
	* gcc.target/arc/nps400-1.c: Likewise.
	* gcc.target/arc/trsub.c: Likewise.
	* gcc.target/arc/barrel-shifter-2.c: Check for barrel
	shifter configuration.
	* gcc.target/arc/mlock.c: Skip for arc6xx
	configurations.
	* gcc.target/arc/mswape.c: Likewise.

From-SVN: r242545

	* config/avr/avr.c (avr_print_operand_address): Use CONST_INT_P if
	appropriate.
	(ashlqi3_out, ashlsi3_out, ashrqi3_out, ashrhi3_out): Same.
	(ashrsi3_out, lshrqi3_out, lshrhi3_out, lshrsi3_out): Same.
	(avr_rtx_costs_1, extra_constraint_Q): Same.
	(avr_address_cost): Use SUBREG_P if possible.

From-SVN: r242544

2016-11-17  Richard Biener  <rguenther@suse.de>

	PR middle-end/78383
	* tree-cfgcleanup.c (cleanup_control_flow_bb): Do not turn
	non-local goto into CFG.

From-SVN: r242543

2016-11-17  Richard Biener  <rguenther@suse.de>

	* common.opt (ftree-loop-if-convert-stores): Mark as preserved for
	backward compatibility.
	* doc/invoke.texi (ftree-loop-if-convert-stores): Remove.
	* tree-if-conv.c (pass_if_conversion::gate): Do not test
	flag_tree_loop_if_convert_stores.
	(pass_if_conversion::execute): Likewise.

From-SVN: r242542

2016-11-17  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/68180
	* g++.dg/cpp1y/pr68180.C: New.

From-SVN: r242541

re PR tree-optimization/78319 (PASS->FAIL: gcc.dg/uninit-pred-8_a.c bogus warning (test for bogus messages, line 20))

2016-11-17  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>

	PR tree-optimization/78319

testsuite/
	* gcc.dg/uninit-pred-8_a.c (foo): Mark dg-bogus test to xfail on
	arm-none-eabi.

From-SVN: r242540

    * config/aarch64/predicates.md (aarch64_reg_or_fp_zero): Check for
    const_double code before calling aarch64_float_const_zero_rtx_p.

From-SVN: r242539

re PR middle-end/78306 ([CilkPlus] "inlining failed in call to always_inline ‘memset’: function not inlinable" with -fcilkplus)

2016-11-17  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/78306
	* ipa-inline-analysis.c (initialize_inline_failed): Do not
	inhibit inlining if function calls cilk_spawn.
	(can_inline_edge_p): Likewise.

	* gcc.dg/cilk-plus/pr78306.c: New testcase.

From-SVN: r242537

2016-11-17  Richard Biener  <rguenther@suse.de>

	PR middle-end/78305
	* fold-const.c (negate_expr_p): Fix multiplication case.

	* gcc.dg/torture/pr78305.c: New testcase.

From-SVN: r242536

re PR fortran/66227 ([OOP] EXTENDS_TYPE_OF n returns wrong result for polymorphic variable allocated to extended type)

2016-11-17  Janus Weil  <janus@gcc.gnu.org>

	PR fortran/66227
	* simplify.c (gfc_simplify_extends_type_of): Fix missed optimization.
	Prevent over-simplification. Fix a comment. Add a comment.

2016-11-17  Janus Weil  <janus@gcc.gnu.org>

	PR fortran/66227
	* gfortran.dg/extends_type_of_3.f90: Fix and extend the test case.

From-SVN: r242535

2016-11-17  Chung-Lin Tang  <cltang@codesourcery.com>

	PR target/78357
	* config/nios2/nios2.c (nios2_init_libfuncs): Remove TARGET_LINUX_ABI
	condition.
	(TARGET_INIT_LIBFUNCS): Delete definition and...
	* config/nios2/linux.h (TARGET_INIT_LIBFUNCS): ...move to here, add
	comments.

From-SVN: r242534

2016-11-17  Krister Walfridsson  <krister.walfridsson@gmail.com>

	* config/netbsd-stdint.h: New.
	* config.gcc (i[34567]86-*-netbsd): Add netbsd-stdint.h to tm_file.
	(x86_64-*-netbsd*): Likewise.

From-SVN: r242533

	PR c/78285
	* c-common.c (c_add_case_label): Turn error_at calls into inform.

	* gcc.dg/switch-5.c: Turn several dg-errors into dg-messages.
	* g++.dg/ext/case-range2.C: Likewise.

From-SVN: r242532

2016-11-16  Andrew PInski  <apinski@cavium.com>

        * config/aarch64/aarch64.opt (mverbose-cost-dump): New option.
        * config/aarch64/aarch64.c (aarch64_rtx_costs): Use
        flag_aarch64_verbose_cost instead of checking for details dump.
        (aarch64_rtx_costs_wrapper): Likewise.

From-SVN: r242531

2016-11-16  Steven G. Kargl  <kargl@gcc.gnu.org>

	PR fortran/58001
	* io.c (next_char_not_space): Update handling of a 'tab' in a FORMAT.
 	(format_lex): Adjust invocations of next_char_not_space().
 
2016-11-16  Steven G. Kargl  <kargl@gcc.gnu.org>

	PR fortran/58001
	* gfortran.dg/fmt_tab_1.f90: Adjust testcase.
	* gfortran.dg/fmt_tab_2.f90: Ditto.

From-SVN: r242530

From-SVN: r242529

	PR rtl-optimization/78378
	* combine.c (make_extraction): Use force_to_mode for non-{REG,MEM}
	inner only if pos is 0.  Fix up formatting.

	* gcc.c-torture/execute/pr78378.c: New test.

From-SVN: r242526

This is a fix for my PR70890 patch, which incorrectly removed all
REG_EQUIV notes rather than just one regarding a reg that dies.

	PR rtl-optimization/78325
	PR rtl-optimization/70890
	* ira.c (combine_and_move_insns): Only remove REG_EQUIV notes
	for dead regno.

From-SVN: r242525