This patch adds support for unwinding frames that use the SVE
pseudo VG register.  We want this register to act like a normal
register if the CFI explicitly sets it, but want to provide a
default value otherwise.  Computing the default value requires
an SVE target, so we only want to compute it on demand.

aarch64_vg uses a hard-coded .inst in order to avoid a build
dependency on binutils 2.28 or later.

2018-01-13  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	* doc/tm.texi.in (DWARF_LAZY_REGISTER_VALUE): Document.
	* doc/tm.texi: Regenerate.

libgcc/
	* config/aarch64/value-unwind.h (aarch64_vg): New function.
	(DWARF_LAZY_REGISTER_VALUE): Define.
	* unwind-dw2.c (_Unwind_GetGR): Use DWARF_LAZY_REGISTER_VALUE
	to provide a fallback register value.

gcc/testsuite/
	* g++.target/aarch64/sve/aarch64-sve.exp: New harness.
	* g++.target/aarch64/sve/catch_1.C: New test.
	* g++.target/aarch64/sve/catch_2.C: Likewise.
	* g++.target/aarch64/sve/catch_3.C: Likewise.
	* g++.target/aarch64/sve/catch_4.C: Likewise.
	* g++.target/aarch64/sve/catch_5.C: Likewise.
	* g++.target/aarch64/sve/catch_6.C: Likewise.

Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>

From-SVN: r256615

This patch adds gcc.target/aarch64 tests for SVE, and forces some
existing Advanced SIMD tests to use -march=armv8-a.

2018-01-13  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/testsuite/
	* lib/target-supports.exp (check_effective_target_aarch64_asm_sve_ok):
	New proc.
	* gcc.target/aarch64/bic_imm_1.c: Use #pragma GCC target "+nosve".
	* gcc.target/aarch64/fmaxmin.c: Likewise.
	* gcc.target/aarch64/fmul_fcvt_2.c: Likewise.
	* gcc.target/aarch64/orr_imm_1.c: Likewise.
	* gcc.target/aarch64/pr62178.c: Likewise.
	* gcc.target/aarch64/pr71727-2.c: Likewise.
	* gcc.target/aarch64/saddw-1.c: Likewise.
	* gcc.target/aarch64/saddw-2.c: Likewise.
	* gcc.target/aarch64/uaddw-1.c: Likewise.
	* gcc.target/aarch64/uaddw-2.c: Likewise.
	* gcc.target/aarch64/uaddw-3.c: Likewise.
	* gcc.target/aarch64/vect-add-sub-cond.c: Likewise.
	* gcc.target/aarch64/vect-compile.c: Likewise.
	* gcc.target/aarch64/vect-faddv-compile.c: Likewise.
	* gcc.target/aarch64/vect-fcm-eq-d.c: Likewise.
	* gcc.target/aarch64/vect-fcm-eq-f.c: Likewise.
	* gcc.target/aarch64/vect-fcm-ge-d.c: Likewise.
	* gcc.target/aarch64/vect-fcm-ge-f.c: Likewise.
	* gcc.target/aarch64/vect-fcm-gt-d.c: Likewise.
	* gcc.target/aarch64/vect-fcm-gt-f.c: Likewise.
	* gcc.target/aarch64/vect-fmax-fmin-compile.c: Likewise.
	* gcc.target/aarch64/vect-fmaxv-fminv-compile.c: Likewise.
	* gcc.target/aarch64/vect-fmovd-zero.c: Likewise.
	* gcc.target/aarch64/vect-fmovd.c: Likewise.
	* gcc.target/aarch64/vect-fmovf-zero.c: Likewise.
	* gcc.target/aarch64/vect-fmovf.c: Likewise.
	* gcc.target/aarch64/vect-fp-compile.c: Likewise.
	* gcc.target/aarch64/vect-ld1r-compile-fp.c: Likewise.
	* gcc.target/aarch64/vect-ld1r-compile.c: Likewise.
	* gcc.target/aarch64/vect-movi.c: Likewise.
	* gcc.target/aarch64/vect-mull-compile.c: Likewise.
	* gcc.target/aarch64/vect-reduc-or_1.c: Likewise.
	* gcc.target/aarch64/vect-vaddv.c: Likewise.
	* gcc.target/aarch64/vect_saddl_1.c: Likewise.
	* gcc.target/aarch64/vect_smlal_1.c: Likewise.
	* gcc.target/aarch64/vector_initialization_nostack.c: XFAIL for
	fixed-length SVE.
	* gcc.target/aarch64/sve/aarch64-sve.exp: New file.
	* gcc.target/aarch64/sve/arith_1.c: New test.
	* gcc.target/aarch64/sve/const_pred_1.C: Likewise.
	* gcc.target/aarch64/sve/const_pred_2.C: Likewise.
	* gcc.target/aarch64/sve/const_pred_3.C: Likewise.
	* gcc.target/aarch64/sve/const_pred_4.C: Likewise.
	* gcc.target/aarch64/sve/cvtf_signed_1.c: Likewise.
	* gcc.target/aarch64/sve/cvtf_signed_1_run.c: Likewise.
	* gcc.target/aarch64/sve/cvtf_unsigned_1.c: Likewise.
	* gcc.target/aarch64/sve/cvtf_unsigned_1_run.c: Likewise.
	* gcc.target/aarch64/sve/dup_imm_1.c: Likewise.
	* gcc.target/aarch64/sve/dup_imm_1_run.c: Likewise.
	* gcc.target/aarch64/sve/dup_lane_1.c: Likewise.
	* gcc.target/aarch64/sve/ext_1.c: Likewise.
	* gcc.target/aarch64/sve/ext_2.c: Likewise.
	* gcc.target/aarch64/sve/extract_1.c: Likewise.
	* gcc.target/aarch64/sve/extract_2.c: Likewise.
	* gcc.target/aarch64/sve/extract_3.c: Likewise.
	* gcc.target/aarch64/sve/extract_4.c: Likewise.
	* gcc.target/aarch64/sve/fabs_1.c: Likewise.
	* gcc.target/aarch64/sve/fcvtz_signed_1.c: Likewise.
	* gcc.target/aarch64/sve/fcvtz_signed_1_run.c: Likewise.
	* gcc.target/aarch64/sve/fcvtz_unsigned_1.c: Likewise.
	* gcc.target/aarch64/sve/fcvtz_unsigned_1_run.c: Likewise.
	* gcc.target/aarch64/sve/fdiv_1.c: Likewise.
	* gcc.target/aarch64/sve/fdup_1.c: Likewise.
	* gcc.target/aarch64/sve/fdup_1_run.c: Likewise.
	* gcc.target/aarch64/sve/fmad_1.c: Likewise.
	* gcc.target/aarch64/sve/fmla_1.c: Likewise.
	* gcc.target/aarch64/sve/fmls_1.c: Likewise.
	* gcc.target/aarch64/sve/fmsb_1.c: Likewise.
	* gcc.target/aarch64/sve/fmul_1.c: Likewise.
	* gcc.target/aarch64/sve/fneg_1.c: Likewise.
	* gcc.target/aarch64/sve/fnmad_1.c: Likewise.
	* gcc.target/aarch64/sve/fnmla_1.c: Likewise.
	* gcc.target/aarch64/sve/fnmls_1.c: Likewise.
	* gcc.target/aarch64/sve/fnmsb_1.c: Likewise.
	* gcc.target/aarch64/sve/fp_arith_1.c: Likewise.
	* gcc.target/aarch64/sve/frinta_1.c: Likewise.
	* gcc.target/aarch64/sve/frinti_1.c: Likewise.
	* gcc.target/aarch64/sve/frintm_1.c: Likewise.
	* gcc.target/aarch64/sve/frintp_1.c: Likewise.
	* gcc.target/aarch64/sve/frintx_1.c: Likewise.
	* gcc.target/aarch64/sve/frintz_1.c: Likewise.
	* gcc.target/aarch64/sve/fsqrt_1.c: Likewise.
	* gcc.target/aarch64/sve/fsubr_1.c: Likewise.
	* gcc.target/aarch64/sve/index_1.c: Likewise.
	* gcc.target/aarch64/sve/index_1_run.c: Likewise.
	* gcc.target/aarch64/sve/ld1r_1.c: Likewise.
	* gcc.target/aarch64/sve/load_const_offset_1.c: Likewise.
	* gcc.target/aarch64/sve/load_const_offset_2.c: Likewise.
	* gcc.target/aarch64/sve/load_const_offset_3.c: Likewise.
	* gcc.target/aarch64/sve/load_scalar_offset_1.c: Likewise.
	* gcc.target/aarch64/sve/logical_1.c: Likewise.
	* gcc.target/aarch64/sve/loop_add_1.c: Likewise.
	* gcc.target/aarch64/sve/loop_add_1_run.c: Likewise.
	* gcc.target/aarch64/sve/mad_1.c: Likewise.
	* gcc.target/aarch64/sve/maxmin_1.c: Likewise.
	* gcc.target/aarch64/sve/maxmin_1_run.c: Likewise.
	* gcc.target/aarch64/sve/maxmin_strict_1.c: Likewise.
	* gcc.target/aarch64/sve/maxmin_strict_1_run.c: Likewise.
	* gcc.target/aarch64/sve/mla_1.c: Likewise.
	* gcc.target/aarch64/sve/mls_1.c: Likewise.
	* gcc.target/aarch64/sve/mov_rr_1.c: Likewise.
	* gcc.target/aarch64/sve/msb_1.c: Likewise.
	* gcc.target/aarch64/sve/mul_1.c: Likewise.
	* gcc.target/aarch64/sve/neg_1.c: Likewise.
	* gcc.target/aarch64/sve/nlogical_1.c: Likewise.
	* gcc.target/aarch64/sve/nlogical_1_run.c: Likewise.
	* gcc.target/aarch64/sve/pack_1.c: Likewise.
	* gcc.target/aarch64/sve/pack_1_run.c: Likewise.
	* gcc.target/aarch64/sve/pack_fcvt_signed_1.c: Likewise.
	* gcc.target/aarch64/sve/pack_fcvt_signed_1_run.c: Likewise.
	* gcc.target/aarch64/sve/pack_fcvt_unsigned_1.c: Likewise.
	* gcc.target/aarch64/sve/pack_fcvt_unsigned_1_run.c: Likewise.
	* gcc.target/aarch64/sve/pack_float_1.c: Likewise.
	* gcc.target/aarch64/sve/pack_float_1_run.c: Likewise.
	* gcc.target/aarch64/sve/popcount_1.c: Likewise.
	* gcc.target/aarch64/sve/popcount_1_run.c: Likewise.
	* gcc.target/aarch64/sve/reduc_1.c: Likewise.
	* gcc.target/aarch64/sve/reduc_1_run.c: Likewise.
	* gcc.target/aarch64/sve/reduc_2.c: Likewise.
	* gcc.target/aarch64/sve/reduc_2_run.c: Likewise.
	* gcc.target/aarch64/sve/reduc_3.c: Likewise.
	* gcc.target/aarch64/sve/rev_1.c: Likewise.
	* gcc.target/aarch64/sve/revb_1.c: Likewise.
	* gcc.target/aarch64/sve/revh_1.c: Likewise.
	* gcc.target/aarch64/sve/revw_1.c: Likewise.
	* gcc.target/aarch64/sve/shift_1.c: Likewise.
	* gcc.target/aarch64/sve/single_1.c: Likewise.
	* gcc.target/aarch64/sve/single_2.c: Likewise.
	* gcc.target/aarch64/sve/single_3.c: Likewise.
	* gcc.target/aarch64/sve/single_4.c: Likewise.
	* gcc.target/aarch64/sve/spill_1.c: Likewise.
	* gcc.target/aarch64/sve/store_scalar_offset_1.c: Likewise.
	* gcc.target/aarch64/sve/subr_1.c: Likewise.
	* gcc.target/aarch64/sve/trn1_1.c: Likewise.
	* gcc.target/aarch64/sve/trn2_1.c: Likewise.
	* gcc.target/aarch64/sve/unpack_fcvt_signed_1.c: Likewise.
	* gcc.target/aarch64/sve/unpack_fcvt_signed_1_run.c: Likewise.
	* gcc.target/aarch64/sve/unpack_fcvt_unsigned_1.c: Likewise.
	* gcc.target/aarch64/sve/unpack_fcvt_unsigned_1_run.c: Likewise.
	* gcc.target/aarch64/sve/unpack_float_1.c: Likewise.
	* gcc.target/aarch64/sve/unpack_float_1_run.c: Likewise.
	* gcc.target/aarch64/sve/unpack_signed_1.c: Likewise.
	* gcc.target/aarch64/sve/unpack_signed_1_run.c: Likewise.
	* gcc.target/aarch64/sve/unpack_unsigned_1.c: Likewise.
	* gcc.target/aarch64/sve/unpack_unsigned_1_run.c: Likewise.
	* gcc.target/aarch64/sve/uzp1_1.c: Likewise.
	* gcc.target/aarch64/sve/uzp1_1_run.c: Likewise.
	* gcc.target/aarch64/sve/uzp2_1.c: Likewise.
	* gcc.target/aarch64/sve/uzp2_1_run.c: Likewise.
	* gcc.target/aarch64/sve/vcond_1.C: Likewise.
	* gcc.target/aarch64/sve/vcond_1_run.C: Likewise.
	* gcc.target/aarch64/sve/vcond_2.c: Likewise.
	* gcc.target/aarch64/sve/vcond_2_run.c: Likewise.
	* gcc.target/aarch64/sve/vcond_3.c: Likewise.
	* gcc.target/aarch64/sve/vcond_4.c: Likewise.
	* gcc.target/aarch64/sve/vcond_4_run.c: Likewise.
	* gcc.target/aarch64/sve/vcond_5.c: Likewise.
	* gcc.target/aarch64/sve/vcond_5_run.c: Likewise.
	* gcc.target/aarch64/sve/vcond_6.c: Likewise.
	* gcc.target/aarch64/sve/vcond_6_run.c: Likewise.
	* gcc.target/aarch64/sve/vec_init_1.c: Likewise.
	* gcc.target/aarch64/sve/vec_init_1_run.c: Likewise.
	* gcc.target/aarch64/sve/vec_init_2.c: Likewise.
	* gcc.target/aarch64/sve/vec_perm_1.c: Likewise.
	* gcc.target/aarch64/sve/vec_perm_1_run.c: Likewise.
	* gcc.target/aarch64/sve/vec_perm_1_overrange_run.c: Likewise.
	* gcc.target/aarch64/sve/vec_perm_const_1.c: Likewise.
	* gcc.target/aarch64/sve/vec_perm_const_1_overrun.c: Likewise.
	* gcc.target/aarch64/sve/vec_perm_const_1_run.c: Likewise.
	* gcc.target/aarch64/sve/vec_perm_const_single_1.c: Likewise.
	* gcc.target/aarch64/sve/vec_perm_const_single_1_run.c: Likewise.
	* gcc.target/aarch64/sve/vec_perm_single_1.c: Likewise.
	* gcc.target/aarch64/sve/vec_perm_single_1_run.c: Likewise.
	* gcc.target/aarch64/sve/zip1_1.c: Likewise.
	* gcc.target/aarch64/sve/zip2_1.c: Likewise.

Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r256614

This patch adds new target selectors for SVE and updates existing
selectors accordingly.  It also XFAILs some tests that don't yet
work for some SVE modes; most of these go away with follow-on
vectorisation enhancements.

2018-01-13  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/testsuite/
	* lib/target-supports.exp (check_effective_target_aarch64_sve)
	(aarch64_sve_bits, check_effective_target_aarch64_sve_hw)
	(aarch64_sve_hw_bits, check_effective_target_aarch64_sve256_hw):
	New procedures.
	(check_effective_target_vect_perm): Handle SVE.
	(check_effective_target_vect_perm_byte): Likewise.
	(check_effective_target_vect_perm_short): Likewise.
	(check_effective_target_vect_widen_sum_hi_to_si_pattern): Likewise.
	(check_effective_target_vect_widen_mult_qi_to_hi): Likewise.
	(check_effective_target_vect_widen_mult_hi_to_si): Likewise.
	(check_effective_target_vect_element_align_preferred): Likewise.
	(check_effective_target_vect_align_stack_vars): Likewise.
	(check_effective_target_vect_load_lanes): Likewise.
	(check_effective_target_vect_masked_store): Likewise.
	(available_vector_sizes): Use aarch64_sve_bits for SVE.
	* gcc.dg/vect/tree-vect.h (VECTOR_BITS): Define appropriately
	for SVE.
	* gcc.dg/tree-ssa/ssa-dom-cse-2.c: Add SVE XFAIL.
	* gcc.dg/vect/bb-slp-pr69907.c: Likewise.
	* gcc.dg/vect/no-vfa-vect-depend-2.c: Likewise.
	* gcc.dg/vect/no-vfa-vect-depend-3.c: Likewise.
	* gcc.dg/vect/slp-23.c: Likewise.
	* gcc.dg/vect/slp-perm-5.c: Likewise.
	* gcc.dg/vect/slp-perm-6.c: Likewise.
	* gcc.dg/vect/slp-perm-9.c: Likewise.
	* gcc.dg/vect/slp-reduc-3.c: Likewise.
	* gcc.dg/vect/vect-114.c: Likewise.
	* gcc.dg/vect/vect-mult-const-pattern-1.c: Likewise.
	* gcc.dg/vect/vect-mult-const-pattern-2.c: Likewise.

Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r256613

This patch adds support for ARM's Scalable Vector Extension.
The patch just contains the core features that work with the
current vectoriser framework; later patches will add extra
capabilities to both the target-independent code and AArch64 code.
The patch doesn't include:

- support for unwinding frames whose size depends on the vector length
- modelling the effect of __tls_get_addr on the SVE registers

These are handled by later patches instead.

Some notes:

- The copyright years for aarch64-sve.md start at 2009 because some of
  the code is based on aarch64.md, which also starts from then.

- The patch inserts spaces between items in the AArch64 section
  of sourcebuild.texi.  This matches at least the surrounding
  architectures and looks a little nicer in the info output.

- aarch64-sve.md includes a pattern:

    while_ult<GPI:mode><PRED_ALL:mode>

  A later patch adds a matching "while_ult" optab, but the pattern
  is also needed by the predicate vec_duplicate expander.

2018-01-13  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* doc/invoke.texi (-msve-vector-bits=): Document new option.
	(sve): Document new AArch64 extension.
	* doc/md.texi (w): Extend the description of the AArch64
	constraint to include SVE vectors.
	(Upl, Upa): Document new AArch64 predicate constraints.
	* config/aarch64/aarch64-opts.h (aarch64_sve_vector_bits_enum): New
	enum.
	* config/aarch64/aarch64.opt (sve_vector_bits): New enum.
	(msve-vector-bits=): New option.
	* config/aarch64/aarch64-option-extensions.def (fp, simd): Disable
	SVE when these are disabled.
	(sve): New extension.
	* config/aarch64/aarch64-modes.def: Define SVE vector and predicate
	modes.  Adjust their number of units based on aarch64_sve_vg.
	(MAX_BITSIZE_MODE_ANY_MODE): Define.
	* config/aarch64/aarch64-protos.h (ADDR_QUERY_ANY): New
	aarch64_addr_query_type.
	(aarch64_const_vec_all_same_in_range_p, aarch64_sve_pred_mode)
	(aarch64_sve_cnt_immediate_p, aarch64_sve_addvl_addpl_immediate_p)
	(aarch64_sve_inc_dec_immediate_p, aarch64_add_offset_temporaries)
	(aarch64_split_add_offset, aarch64_output_sve_cnt_immediate)
	(aarch64_output_sve_addvl_addpl, aarch64_output_sve_inc_dec_immediate)
	(aarch64_output_sve_mov_immediate, aarch64_output_ptrue): Declare.
	(aarch64_simd_imm_zero_p): Delete.
	(aarch64_check_zero_based_sve_index_immediate): Declare.
	(aarch64_sve_index_immediate_p, aarch64_sve_arith_immediate_p)
	(aarch64_sve_bitmask_immediate_p, aarch64_sve_dup_immediate_p)
	(aarch64_sve_cmp_immediate_p, aarch64_sve_float_arith_immediate_p)
	(aarch64_sve_float_mul_immediate_p): Likewise.
	(aarch64_classify_symbol): Take the offset as a HOST_WIDE_INT
	rather than an rtx.
	(aarch64_sve_ld1r_operand_p, aarch64_sve_ldr_operand_p): Declare.
	(aarch64_expand_mov_immediate): Take a gen_vec_duplicate callback.
	(aarch64_emit_sve_pred_move, aarch64_expand_sve_mem_move): Declare.
	(aarch64_expand_sve_vec_cmp_int, aarch64_expand_sve_vec_cmp_float)
	(aarch64_expand_sve_vcond, aarch64_expand_sve_vec_perm): Declare.
	(aarch64_regmode_natural_size): Likewise.
	* config/aarch64/aarch64.h (AARCH64_FL_SVE): New macro.
	(AARCH64_FL_V8_3, AARCH64_FL_RCPC, AARCH64_FL_DOTPROD): Shift
	left one place.
	(AARCH64_ISA_SVE, TARGET_SVE): New macros.
	(FIXED_REGISTERS, CALL_USED_REGISTERS, REGISTER_NAMES): Add entries
	for VG and the SVE predicate registers.
	(V_ALIASES): Add a "z"-prefixed alias.
	(FIRST_PSEUDO_REGISTER): Change to P15_REGNUM + 1.
	(AARCH64_DWARF_VG, AARCH64_DWARF_P0): New macros.
	(PR_REGNUM_P, PR_LO_REGNUM_P): Likewise.
	(PR_LO_REGS, PR_HI_REGS, PR_REGS): New reg_classes.
	(REG_CLASS_NAMES): Add entries for them.
	(REG_CLASS_CONTENTS): Likewise.  Update ALL_REGS to include VG
	and the predicate registers.
	(aarch64_sve_vg): Declare.
	(BITS_PER_SVE_VECTOR, BYTES_PER_SVE_VECTOR, BYTES_PER_SVE_PRED)
	(SVE_BYTE_MODE, MAX_COMPILE_TIME_VEC_BYTES): New macros.
	(REGMODE_NATURAL_SIZE): Define.
	* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Handle
	SVE macros.
	* config/aarch64/aarch64.c: Include cfgrtl.h.
	(simd_immediate_info): Add a constructor for series vectors,
	and an associated step field.
	(aarch64_sve_vg): New variable.
	(aarch64_dbx_register_number): Handle VG and the predicate registers.
	(aarch64_vect_struct_mode_p, aarch64_vector_mode_p): Delete.
	(VEC_ADVSIMD, VEC_SVE_DATA, VEC_SVE_PRED, VEC_STRUCT, VEC_ANY_SVE)
	(VEC_ANY_DATA, VEC_STRUCT): New constants.
	(aarch64_advsimd_struct_mode_p, aarch64_sve_pred_mode_p)
	(aarch64_classify_vector_mode, aarch64_vector_data_mode_p)
	(aarch64_sve_data_mode_p, aarch64_sve_pred_mode)
	(aarch64_get_mask_mode): New functions.
	(aarch64_hard_regno_nregs): Handle SVE data modes for FP_REGS
	and FP_LO_REGS.  Handle PR_REGS, PR_LO_REGS and PR_HI_REGS.
	(aarch64_hard_regno_mode_ok): Handle VG.  Also handle the SVE
	predicate modes and predicate registers.  Explicitly restrict
	GPRs to modes of 16 bytes or smaller.  Only allow FP registers
	to store a vector mode if it is recognized by
	aarch64_classify_vector_mode.
	(aarch64_regmode_natural_size): New function.
	(aarch64_hard_regno_caller_save_mode): Return the original mode
	for predicates.
	(aarch64_sve_cnt_immediate_p, aarch64_output_sve_cnt_immediate)
	(aarch64_sve_addvl_addpl_immediate_p, aarch64_output_sve_addvl_addpl)
	(aarch64_sve_inc_dec_immediate_p, aarch64_output_sve_inc_dec_immediate)
	(aarch64_add_offset_1_temporaries, aarch64_offset_temporaries): New
	functions.
	(aarch64_add_offset): Add a temp2 parameter.  Assert that temp1
	does not overlap dest if the function is frame-related.  Handle
	SVE constants.
	(aarch64_split_add_offset): New function.
	(aarch64_add_sp, aarch64_sub_sp): Add temp2 parameters and pass
	them aarch64_add_offset.
	(aarch64_allocate_and_probe_stack_space): Add a temp2 parameter
	and update call to aarch64_sub_sp.
	(aarch64_add_cfa_expression): New function.
	(aarch64_expand_prologue): Pass extra temporary registers to the
	functions above.  Handle the case in which we need to emit new
	DW_CFA_expressions for registers that were originally saved
	relative to the stack pointer, but now have to be expressed
	relative to the frame pointer.
	(aarch64_output_mi_thunk): Pass extra temporary registers to the
	functions above.
	(aarch64_expand_epilogue): Likewise.  Prevent inheritance of
	IP0 and IP1 values for SVE frames.
	(aarch64_expand_vec_series): New function.
	(aarch64_expand_sve_widened_duplicate): Likewise.
	(aarch64_expand_sve_const_vector): Likewise.
	(aarch64_expand_mov_immediate): Add a gen_vec_duplicate parameter.
	Handle SVE constants.  Use emit_move_insn to move a force_const_mem
	into the register, rather than emitting a SET directly.
	(aarch64_emit_sve_pred_move, aarch64_expand_sve_mem_move)
	(aarch64_get_reg_raw_mode, offset_4bit_signed_scaled_p)
	(offset_6bit_unsigned_scaled_p, aarch64_offset_7bit_signed_scaled_p)
	(offset_9bit_signed_scaled_p): New functions.
	(aarch64_replicate_bitmask_imm): New function.
	(aarch64_bitmask_imm): Use it.
	(aarch64_cannot_force_const_mem): Reject expressions involving
	a CONST_POLY_INT.  Update call to aarch64_classify_symbol.
	(aarch64_classify_index): Handle SVE indices, by requiring
	a plain register index with a scale that matches the element size.
	(aarch64_classify_address): Handle SVE addresses.  Assert that
	the mode of the address is VOIDmode or an integer mode.
	Update call to aarch64_classify_symbol.
	(aarch64_classify_symbolic_expression): Update call to
	aarch64_classify_symbol.
	(aarch64_const_vec_all_in_range_p): New function.
	(aarch64_print_vector_float_operand): Likewise.
	(aarch64_print_operand): Handle 'N' and 'C'.  Use "zN" rather than
	"vN" for FP registers with SVE modes.  Handle (const ...) vectors
	and the FP immediates 1.0 and 0.5.
	(aarch64_print_address_internal): Handle SVE addresses.
	(aarch64_print_operand_address): Use ADDR_QUERY_ANY.
	(aarch64_regno_regclass): Handle predicate registers.
	(aarch64_secondary_reload): Handle big-endian reloads of SVE
	data modes.
	(aarch64_class_max_nregs): Handle SVE modes and predicate registers.
	(aarch64_rtx_costs): Check for ADDVL and ADDPL instructions.
	(aarch64_convert_sve_vector_bits): New function.
	(aarch64_override_options): Use it to handle -msve-vector-bits=.
	(aarch64_classify_symbol): Take the offset as a HOST_WIDE_INT
	rather than an rtx.
	(aarch64_legitimate_constant_p): Use aarch64_classify_vector_mode.
	Handle SVE vector and predicate modes.  Accept VL-based constants
	that need only one temporary register, and VL offsets that require
	no temporary registers.
	(aarch64_conditional_register_usage): Mark the predicate registers
	as fixed if SVE isn't available.
	(aarch64_vector_mode_supported_p): Use aarch64_classify_vector_mode.
	Return true for SVE vector and predicate modes.
	(aarch64_simd_container_mode): Take the number of bits as a poly_int64
	rather than an unsigned int.  Handle SVE modes.
	(aarch64_preferred_simd_mode): Update call accordingly.  Handle
	SVE modes.
	(aarch64_autovectorize_vector_sizes): Add BYTES_PER_SVE_VECTOR
	if SVE is enabled.
	(aarch64_sve_index_immediate_p, aarch64_sve_arith_immediate_p)
	(aarch64_sve_bitmask_immediate_p, aarch64_sve_dup_immediate_p)
	(aarch64_sve_cmp_immediate_p, aarch64_sve_float_arith_immediate_p)
	(aarch64_sve_float_mul_immediate_p): New functions.
	(aarch64_sve_valid_immediate): New function.
	(aarch64_simd_valid_immediate): Use it as the fallback for SVE vectors.
	Explicitly reject structure modes.  Check for INDEX constants.
	Handle PTRUE and PFALSE constants.
	(aarch64_check_zero_based_sve_index_immediate): New function.
	(aarch64_simd_imm_zero_p): Delete.
	(aarch64_mov_operand_p): Use aarch64_simd_valid_immediate for
	vector modes.  Accept constants in the range of CNT[BHWD].
	(aarch64_simd_scalar_immediate_valid_for_move): Explicitly
	ask for an Advanced SIMD mode.
	(aarch64_sve_ld1r_operand_p, aarch64_sve_ldr_operand_p): New functions.
	(aarch64_simd_vector_alignment): Handle SVE predicates.
	(aarch64_vectorize_preferred_vector_alignment): New function.
	(aarch64_simd_vector_alignment_reachable): Use it instead of
	the vector size.
	(aarch64_shift_truncation_mask): Use aarch64_vector_data_mode_p.
	(aarch64_output_sve_mov_immediate, aarch64_output_ptrue): New
	functions.
	(MAX_VECT_LEN): Delete.
	(expand_vec_perm_d): Add a vec_flags field.
	(emit_unspec2, aarch64_expand_sve_vec_perm): New functions.
	(aarch64_evpc_trn, aarch64_evpc_uzp, aarch64_evpc_zip)
	(aarch64_evpc_ext): Don't apply a big-endian lane correction
	for SVE modes.
	(aarch64_evpc_rev): Rename to...
	(aarch64_evpc_rev_local): ...this.  Use a predicated operation for SVE.
	(aarch64_evpc_rev_global): New function.
	(aarch64_evpc_dup): Enforce a 64-byte range for SVE DUP.
	(aarch64_evpc_tbl): Use MAX_COMPILE_TIME_VEC_BYTES instead of
	MAX_VECT_LEN.
	(aarch64_evpc_sve_tbl): New function.
	(aarch64_expand_vec_perm_const_1): Update after rename of
	aarch64_evpc_rev.  Handle SVE permutes too, trying
	aarch64_evpc_rev_global and using aarch64_evpc_sve_tbl rather
	than aarch64_evpc_tbl.
	(aarch64_vectorize_vec_perm_const): Initialize vec_flags.
	(aarch64_sve_cmp_operand_p, aarch64_unspec_cond_code)
	(aarch64_gen_unspec_cond, aarch64_expand_sve_vec_cmp_int)
	(aarch64_emit_unspec_cond, aarch64_emit_unspec_cond_or)
	(aarch64_emit_inverted_unspec_cond, aarch64_expand_sve_vec_cmp_float)
	(aarch64_expand_sve_vcond): New functions.
	(aarch64_modes_tieable_p): Use aarch64_vector_data_mode_p instead
	of aarch64_vector_mode_p.
	(aarch64_dwarf_poly_indeterminate_value): New function.
	(aarch64_compute_pressure_classes): Likewise.
	(aarch64_can_change_mode_class): Likewise.
	(TARGET_GET_RAW_RESULT_MODE, TARGET_GET_RAW_ARG_MODE): Redefine.
	(TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT): Likewise.
	(TARGET_VECTORIZE_GET_MASK_MODE): Likewise.
	(TARGET_DWARF_POLY_INDETERMINATE_VALUE): Likewise.
	(TARGET_COMPUTE_PRESSURE_CLASSES): Likewise.
	(TARGET_CAN_CHANGE_MODE_CLASS): Likewise.
	* config/aarch64/constraints.md (Upa, Upl, Uav, Uat, Usv, Usi, Utr)
	(Uty, Dm, vsa, vsc, vsd, vsi, vsn, vsl, vsm, vsA, vsM, vsN): New
	constraints.
	(Dn, Dl, Dr): Accept const as well as const_vector.
	(Dz): Likewise.  Compare against CONST0_RTX.
	* config/aarch64/iterators.md: Refer to "Advanced SIMD" instead
	of "vector" where appropriate.
	(SVE_ALL, SVE_BH, SVE_BHS, SVE_BHSI, SVE_HSDI, SVE_HSF, SVE_SD)
	(SVE_SDI, SVE_I, SVE_F, PRED_ALL, PRED_BHS): New mode iterators.
	(UNSPEC_SEL, UNSPEC_ANDF, UNSPEC_IORF, UNSPEC_XORF, UNSPEC_COND_LT)
	(UNSPEC_COND_LE, UNSPEC_COND_EQ, UNSPEC_COND_NE, UNSPEC_COND_GE)
	(UNSPEC_COND_GT, UNSPEC_COND_LO, UNSPEC_COND_LS, UNSPEC_COND_HS)
	(UNSPEC_COND_HI, UNSPEC_COND_UO): New unspecs.
	(Vetype, VEL, Vel, VWIDE, Vwide, vw, vwcore, V_INT_EQUIV)
	(v_int_equiv): Extend to SVE modes.
	(Vesize, V128, v128, Vewtype, V_FP_EQUIV, v_fp_equiv, VPRED): New
	mode attributes.
	(LOGICAL_OR, SVE_INT_UNARY, SVE_FP_UNARY): New code iterators.
	(optab): Handle popcount, smin, smax, umin, umax, abs and sqrt.
	(logical_nn, lr, sve_int_op, sve_fp_op): New code attributs.
	(LOGICALF, OPTAB_PERMUTE, UNPACK, UNPACK_UNSIGNED, SVE_COND_INT_CMP)
	(SVE_COND_FP_CMP): New int iterators.
	(perm_hilo): Handle the new unpack unspecs.
	(optab, logicalf_op, su, perm_optab, cmp_op, imm_con): New int
	attributes.
	* config/aarch64/predicates.md (aarch64_sve_cnt_immediate)
	(aarch64_sve_addvl_addpl_immediate, aarch64_split_add_offset_immediate)
	(aarch64_pluslong_or_poly_operand, aarch64_nonmemory_operand)
	(aarch64_equality_operator, aarch64_constant_vector_operand)
	(aarch64_sve_ld1r_operand, aarch64_sve_ldr_operand): New predicates.
	(aarch64_sve_nonimmediate_operand): Likewise.
	(aarch64_sve_general_operand): Likewise.
	(aarch64_sve_dup_operand, aarch64_sve_arith_immediate): Likewise.
	(aarch64_sve_sub_arith_immediate, aarch64_sve_inc_dec_immediate)
	(aarch64_sve_logical_immediate, aarch64_sve_mul_immediate): Likewise.
	(aarch64_sve_dup_immediate, aarch64_sve_cmp_vsc_immediate): Likewise.
	(aarch64_sve_cmp_vsd_immediate, aarch64_sve_index_immediate): Likewise.
	(aarch64_sve_float_arith_immediate): Likewise.
	(aarch64_sve_float_arith_with_sub_immediate): Likewise.
	(aarch64_sve_float_mul_immediate, aarch64_sve_arith_operand): Likewise.
	(aarch64_sve_add_operand, aarch64_sve_logical_operand): Likewise.
	(aarch64_sve_lshift_operand, aarch64_sve_rshift_operand): Likewise.
	(aarch64_sve_mul_operand, aarch64_sve_cmp_vsc_operand): Likewise.
	(aarch64_sve_cmp_vsd_operand, aarch64_sve_index_operand): Likewise.
	(aarch64_sve_float_arith_operand): Likewise.
	(aarch64_sve_float_arith_with_sub_operand): Likewise.
	(aarch64_sve_float_mul_operand): Likewise.
	(aarch64_sve_vec_perm_operand): Likewise.
	(aarch64_pluslong_operand): Include aarch64_sve_addvl_addpl_immediate.
	(aarch64_mov_operand): Accept const_poly_int and const_vector.
	(aarch64_simd_lshift_imm, aarch64_simd_rshift_imm): Accept const
	as well as const_vector.
	(aarch64_simd_imm_zero, aarch64_simd_imm_minus_one): Move earlier
	in file.  Use CONST0_RTX and CONSTM1_RTX.
	(aarch64_simd_or_scalar_imm_zero): Likewise.  Add match_codes.
	(aarch64_simd_reg_or_zero): Accept const as well as const_vector.
	Use aarch64_simd_imm_zero.
	* config/aarch64/aarch64-sve.md: New file.
	* config/aarch64/aarch64.md: Include it.
	(VG_REGNUM, P0_REGNUM, P7_REGNUM, P15_REGNUM): New register numbers.
	(UNSPEC_REV, UNSPEC_LD1_SVE, UNSPEC_ST1_SVE, UNSPEC_MERGE_PTRUE)
	(UNSPEC_PTEST_PTRUE, UNSPEC_UNPACKSHI, UNSPEC_UNPACKUHI)
	(UNSPEC_UNPACKSLO, UNSPEC_UNPACKULO, UNSPEC_PACK)
	(UNSPEC_FLOAT_CONVERT, UNSPEC_WHILE_LO): New unspec constants.
	(sve): New attribute.
	(enabled): Disable instructions with the sve attribute unless
	TARGET_SVE.
	(movqi, movhi): Pass CONST_POLY_INT operaneds through
	aarch64_expand_mov_immediate.
	(*mov<mode>_aarch64, *movsi_aarch64, *movdi_aarch64): Handle
	CNT[BHSD] immediates.
	(movti): Split CONST_POLY_INT moves into two halves.
	(add<mode>3): Accept aarch64_pluslong_or_poly_operand.
	Split additions that need a temporary here if the destination
	is the stack pointer.
	(*add<mode>3_aarch64): Handle ADDVL and ADDPL immediates.
	(*add<mode>3_poly_1): New instruction.
	(set_clobber_cc): New expander.

Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r256612

Until SLP support for variable-length vectors is added, many tests
fall back to non-SLP vectorisation with permutes.

2018-01-13  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/testsuite/
	* gcc.dg/vect/no-scevccp-slp-30.c: XFAIL SLP test for
	vect_variable_length, expecting the test to be vectorized
	without SLP instead.
	* gcc.dg/vect/pr33953.c: Likewise.
	* gcc.dg/vect/pr37027.c: Likewise.
	* gcc.dg/vect/pr67790.c: Likewise.
	* gcc.dg/vect/pr68445.c: Likewise.
	* gcc.dg/vect/slp-1.c: Likewise.
	* gcc.dg/vect/slp-10.c: Likewise.
	* gcc.dg/vect/slp-12a.c: Likewise.
	* gcc.dg/vect/slp-12b.c: Likewise.
	* gcc.dg/vect/slp-12c.c: Likewise.
	* gcc.dg/vect/slp-13-big-array.c: Likewise.
	* gcc.dg/vect/slp-13.c: Likewise.
	* gcc.dg/vect/slp-14.c: Likewise.
	* gcc.dg/vect/slp-15.c: Likewise.
	* gcc.dg/vect/slp-17.c: Likewise.
	* gcc.dg/vect/slp-19b.c: Likewise.
	* gcc.dg/vect/slp-2.c: Likewise.
	* gcc.dg/vect/slp-20.c: Likewise.
	* gcc.dg/vect/slp-21.c: Likewise.
	* gcc.dg/vect/slp-22.c: Likewise.
	* gcc.dg/vect/slp-24-big-array.c: Likewise.
	* gcc.dg/vect/slp-24.c: Likewise.
	* gcc.dg/vect/slp-28.c: Likewise.
	* gcc.dg/vect/slp-39.c: Likewise.
	* gcc.dg/vect/slp-42.c: Likewise.
	* gcc.dg/vect/slp-6.c: Likewise.
	* gcc.dg/vect/slp-7.c: Likewise.
	* gcc.dg/vect/slp-cond-1.c: Likewise.
	* gcc.dg/vect/slp-cond-2-big-array.c: Likewise.
	* gcc.dg/vect/slp-cond-2.c: Likewise.
	* gcc.dg/vect/slp-multitypes-1.c: Likewise.
	* gcc.dg/vect/slp-multitypes-10.c: Likewise.
	* gcc.dg/vect/slp-multitypes-12.c: Likewise.
	* gcc.dg/vect/slp-multitypes-2.c: Likewise.
	* gcc.dg/vect/slp-multitypes-4.c: Likewise.
	* gcc.dg/vect/slp-multitypes-5.c: Likewise.
	* gcc.dg/vect/slp-multitypes-8.c: Likewise.
	* gcc.dg/vect/slp-multitypes-9.c: Likewise.
	* gcc.dg/vect/slp-reduc-1.c: Likewise.
	* gcc.dg/vect/slp-reduc-2.c: Likewise.
	* gcc.dg/vect/slp-reduc-4.c: Likewise.
	* gcc.dg/vect/slp-reduc-5.c: Likewise.
	* gcc.dg/vect/slp-reduc-7.c: Likewise.
	* gcc.dg/vect/slp-widen-mult-half.c: Likewise.
	* gcc.dg/vect/vect-live-slp-1.c: Likewise.
	* gcc.dg/vect/vect-live-slp-2.c: Likewise.
	* gcc.dg/vect/vect-live-slp-3.c: Likewise.

From-SVN: r256611

The SVE support for the new CONST_VECTOR encoding needs to be able
to extract the first N bits of the vector and duplicate it.  This patch
adds a simplify_subreg rule for that.

The code is covered by the gcc.target/aarch64/sve_slp_*.c tests.

2018-01-13  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	* simplify-rtx.c (simplify_immed_subreg): Add an inner_bytes
	parameter and use it instead of GET_MODE_SIZE (innermode).  Use
	inner_bytes * BITS_PER_UNIT instead of GET_MODE_BITSIZE (innermode).
	Use CEIL (inner_bytes, GET_MODE_UNIT_SIZE (innermode)) instead of
	GET_MODE_NUNITS (innermode).  Also add a first_elem parameter.
	Change innermode from fixed_mode_size to machine_mode.
	(simplify_subreg): Update call accordingly.  Handle a constant-sized
	subreg of a variable-length CONST_VECTOR.

From-SVN: r256610

A general TARGET_MEM_REF is:

    BASE + STEP * INDEX + INDEX2 + OFFSET

After classifying the address in this way, the code that builds
TARGET_MEM_REFs tries to simplify the address until it's valid
for the current target and for the mode of memory being addressed.
It does this in a fixed order:

(1) add SYMBOL to BASE
(2) add INDEX * STEP to the base, if STEP != 1
(3) add OFFSET to INDEX or BASE (reverted if unsuccessful)
(4) add INDEX to BASE
(5) add OFFSET to BASE

So suppose we had an address:

    &symbol + offset + index * 8

(e.g. a[i + 1] for a global "a") on a target only allows an index or an
offset, not both.  Following the steps above, we'd first create:

    tmp = symbol
    tmp2 = tmp + index * 8

Then if the given offset value was valid for the mode being addressed,
we'd create:

    MEM[base:tmp2, offset:offset]

while if it was invalid we'd create:

    tmp3 = tmp2 + offset
    MEM[base:tmp3, offset:0]

The problem is that this could happen if ivopts had decided to use
a scaled index for an address that happens to have a constant base.
The old procedure failed to give an indexed TARGET_MEM_REF in that case,
and adding the offset last prevented later passes from being able to
fold the index back in.

The patch avoids this by checking at (2) whether the offset is the
only component that causes the address to be invalid, folding it
into the base if so.

2018-01-13  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* tree-ssa-address.c (mem_ref_valid_without_offset_p): New function.
	(add_offset_to_base): New function, split out from...
	(create_mem_ref): ...here.  When handling a scale other than 1,
	check first whether the address is valid without the offset.
	Add it into the base if so, leaving the index and scale as-is.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r256609

	PR c/83801
	* c-tree.h (decl_constant_value_1): Add a bool argument.
	* c-typeck.c (decl_constant_value_1): Add IN_INIT argument, allow
	returning a CONSTRUCTOR if it is true.  Use error_operand_p.
	(decl_constant_value): Adjust caller.
	* c-fold.c (c_fully_fold_internal): If in_init, pass true to
	decl_constant_value_1 as IN_INIT.  Otherwise, punt if
	decl_constant_value returns initializer that has BLKmode or
	array type.
	(c_fully_fold_internal) <case COMPONENT_REF>: Fold if !lval.

	* gcc.dg/pr83801.c: New test.

From-SVN: r256608

2018-01-13  Paul Thomas  <pault@gcc.gnu.org>

	PR fortran/52162
	* trans-expr.c (gfc_trans_scalar_assign): Flag is_alloc_lhs if
	the rhs expression is neither an elemental nor a conversion
	function.

	PR fortran/83622
	* trans-array.c (is_pointer_array): Remove unconditional return
	of false for -fopenmp.

2018-01-13  Paul Thomas  <pault@gcc.gnu.org>

	PR fortran/52162
	* gfortran.dg/bounds_check_19.f90 : New test.

From-SVN: r256607

re PR fortran/83803 (Using -fc-prototypes on modules with empty dummy arg lists does not close paren.)

2018-01-13  Thomas Koenig <tkoenig@gcc.gnu.org>
	<emsr@gcc.gnu.org>

	PR fortran/83803
	* dump-parse-tree.c (write_proc): Always emit closing parenthesis
	for functions.

From-SVN: r256606

From-SVN: r256602

	PR c++/83778
	* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Call
	fold_for_warn before checking if arg2 is INTEGER_CST.

From-SVN: r256599

-mstring is only enabled by default on 601, and with -Os on some
configurations.  It is almost always slower (than not using it) and
does not very often lead to smaller code.

This patch disables it.  If a user uses -mstring he gets a warning
(but not with -mno-string).  I left the target attribute in place, it
just doesn't do anything anymore.

The patch also deletes a whole bunch of code.  The 'N' and 'O' output
modifiers are now unused, but now is not the time to delete them.


	* config/rs6000/predicates.md (load_multiple_operation): Delete.
	(store_multiple_operation): Delete.
	* config/rs6000/rs6000-cpus.def (601): Remove MASK_STRING.
	* config/rs6000/rs6000-protos.h (rs6000_output_load_multiple): Delete.
	* config/rs6000/rs6000-string.c (expand_block_move): Delete everything
	guarded by TARGET_STRING.
	(rs6000_output_load_multiple): Delete.
	* config/rs6000/rs6000.c (rs6000_option_override_internal): Delete
	OPTION_MASK_STRING / TARGET_STRING handling.
	(print_operand) <'N', 'O'>: Add comment that these are unused now.
	(const rs6000_opt_masks) <"string">: Change mask to 0.
	* config/rs6000/rs6000.h (TARGET_DEFAULT): Remove MASK_STRING.
	(MASK_STRING): Delete.
	* config/rs6000/rs6000.md (*mov<mode>_string): Delete TARGET_STRING
	parts.  Simplify.
	(load_multiple): Delete.
	(*ldmsi8): Delete.
	(*ldmsi7): Delete.
	(*ldmsi6): Delete.
	(*ldmsi5): Delete.
	(*ldmsi4): Delete.
	(*ldmsi3): Delete.
	(store_multiple): Delete.
	(*stmsi8): Delete.
	(*stmsi7): Delete.
	(*stmsi6): Delete.
	(*stmsi5): Delete.
	(*stmsi4): Delete.
	(*stmsi3): Delete.
	(movmemsi_8reg): Delete.
	(corresponding unnamed define_insn): Delete.
	(movmemsi_6reg): Delete.
	(corresponding unnamed define_insn): Delete.
	(movmemsi_4reg): Delete.
	(corresponding unnamed define_insn): Delete.
	(movmemsi_2reg): Delete.
	(corresponding unnamed define_insn): Delete.
	(movmemsi_1reg): Delete.
	(corresponding unnamed define_insn): Delete.
	* config/rs6000/rs6000.opt (mno-string): New.
	(mstring): Replace by deprecation warning stub.
	* doc/invoke.texi (RS/6000 and PowerPC Options): Delete -mstring.

From-SVN: r256598

	* gcc.target/powerpc/float128-hw7.c: Use scan-assembler-times
	instead of scan-assembler-not for xsnabsqp.

From-SVN: r256597

regrename.c (regrename_do_replace): If replacing the same reg multiple times, try to reuse last created gen_raw_REG.

	* regrename.c (regrename_do_replace): If replacing the same
	reg multiple times, try to reuse last created gen_raw_REG.

From-SVN: r256596

re PR fortran/83525 (open(newunit=funit, status="scratch") fails if an internal file (characters) was read previously.)

2018-01-12  Jerry DeLisle  <jvdelisle@gcc.gnu.org>

        PR libgfortran/83525
        * gfortran.dg/newunit_5.f90: New test.

From-SVN: r256595

	* typeck.c (build_static_cast): Use build_non_dependent_expr.

From-SVN: r256594

https://gcc.gnu.org/ml/gcc-patches/2018-01/msg01107.html
	* cp-tree.h (mark_rvalue_use): Add parm name.
	* expr.c (mark_lvalue_use, mark_lvalue_use_nonread): Move next to
	mark_rvalue_use.
	* call.c (convert_like_real): Fix formatting.

From-SVN: r256593

	PR debug/81155
	* bb-reorder.c (pass_partition_blocks::gate): In lto don't partition
	main to workaround a bug in GDB.

From-SVN: r256592

2018-01-12  Tom de Vries  <tom@codesourcery.com>

	PR target/83737
	* config.gcc (nvptx*-*-*): Set use_gcc_stdint=wrap.

From-SVN: r256591

2018-01-12  Vladimir Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/80481
	* ira-color.c (get_cap_member): New function.
	(allocnos_conflict_by_live_ranges_p): Use it.
	(slot_coalesced_allocno_live_ranges_intersect_p): Add assert.
	(setup_slot_coalesced_allocno_live_ranges): Ditto.

2018-01-12  Vladimir Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/80481
	* g++.dg/pr80481.C: New.

From-SVN: r256590

	PR target/83628
	* config/alpha/alpha.md (*saddsi_1): New insn_ans_split pattern.
	(*saddl_se_1): Ditto.
	(*ssubsi_1): Ditto.
	(*saddl_se_1): Ditto.

testsuite/ChangeLog:

	PR target/83628
	* gcc.target/alpha/pr83628-3.c: New test.

From-SVN: r256589

	* lib/target-supports.exp (check_effective_target_avx512f): Also
	check for __builtin_ia32_addsd_round,
	__builtin_ia32_getmantsd_round.
	* gcc.target/i386/i386.exp (check_effective_target_avx512f):
	Remove.

From-SVN: r256588

The idea with the main 107-patch poly_int series (latterly 109-patch)
was to change the mode sizes and vector element counts to poly_int and
then propagate those changes as far as they needed to go to fix build
failures from incompatible types.  This means that DR_INIT is now
constructed as a poly_int64:

  poly_int64 pbytepos;
  if (!multiple_p (pbitpos, BITS_PER_UNIT, &pbytepos))
    {
      if (dump_file && (dump_flags & TDF_DETAILS))
	fprintf (dump_file, "failed: bit offset alignment.\n");
      return false;
    }
  [...]
  init = ssize_int (pbytepos);

This patch adjusts other references to DR_INIT accordingly.  Unlike
the above, the adjustments weren't needed to avoid a build-time type
incompatibility, but they are needed to make the producer and consumers
of DR_INIT logically consistent.

2018-01-12  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	* tree-predcom.c (aff_combination_dr_offset): Use wi::to_poly_widest
	rather than wi::to_widest for DR_INITs.
	* tree-vect-data-refs.c (vect_find_same_alignment_drs): Use
	wi::to_poly_offset rather than wi::to_offset for DR_INIT.
	(vect_analyze_data_ref_accesses): Require both DR_INITs to be
	INTEGER_CSTs.
	(vect_analyze_group_access_1): Note that here.

From-SVN: r256587

get_vectype_for_scalar_type returns a variable-length vector type
for SVE, whereas get_vec_alignment_for_array_type assumed it would
always be an INTEGER_CST.

This is needed to build libstdc++-v3/src/closures.cc for SVE
(and probably many other places besides -- this was just the
first hit).

2018-01-12  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	* tree-vectorizer.c (get_vec_alignment_for_array_type): Handle
	polynomial type sizes.

From-SVN: r256586

This is needed to build libgfortran for SVE.  The OpenMP code needs
to create temporary vector variables, and the variables will therefore
be variable-sized for SVE.  Earlier patches made such variables work.

2018-01-12  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	* gimplify.c (gimple_add_tmp_var_fn): Allow variables to have a
	poly_uint64 size, rather than requiring an unsigned HOST_WIDE_INT size.
	(gimple_add_tmp_var): Likewise.

From-SVN: r256585

2018-01-12  Martin Liska  <mliska@suse.cz>

	* gimple.c (gimple_alloc_counts): Use uint64_t instead of int.
	(gimple_alloc_sizes): Likewise.
	(dump_gimple_statistics): Use PRIu64 in printf format.
	* gimple.h: Change uint64_t to int.

From-SVN: r256584

2018-01-12  Martin Liska  <mliska@suse.cz>

	* tree-core.h: Use uint64_t instead of int.
	* tree.c (tree_node_counts): Likewise.
	(tree_node_sizes): Likewise.
	(dump_tree_statistics): Use PRIu64 in printf format.

From-SVN: r256583

2018-01-12  Martin Liska  <mliska@suse.cz>

	* Makefile.in: As qsort_chk is implemented in vec.c, add
	vec.o to linkage of gencfn-macros.
	* tree.c (build_new_poly_int_cst): Add CXX_MEM_STAT_INFO as it's
	passing the info to record_node_allocation_statistics.
	(test_vector_cst_patterns): Add CXX_MEM_STAT_INFO to declaration
	and pass the info.
	* ggc-common.c (struct ggc_usage): Add operator== and use
	it in operator< and compare function.
	* mem-stats.h (struct mem_usage): Likewise.
	* vec.c (struct vec_usage): Remove operator< and compare
	function. Can be simply inherited.

From-SVN: r256582

2018-01-12  Martin Jambor  <mjambor@suse.cz>

	PR target/81616
	* params.def: New parameter PARAM_AVOID_FMA_MAX_BITS.
	* tree-ssa-math-opts.c: Include domwalk.h.
	(convert_mult_to_fma_1): New function.
	(fma_transformation_info): New type.
	(fma_deferring_state): Likewise.
	(cancel_fma_deferring): New function.
	(result_of_phi): Likewise.
	(last_fma_candidate_feeds_initial_phi): Likewise.
	(convert_mult_to_fma): Added deferring logic, split actual
	transformation to convert_mult_to_fma_1.
	(math_opts_dom_walker): New type.
	(math_opts_dom_walker::after_dom_children): New method, body moved
	here from pass_optimize_widening_mul::execute, added deferring logic
	bits.
	(pass_optimize_widening_mul::execute): Moved most of code to
	math_opts_dom_walker::after_dom_children.
	* config/i386/x86-tune.def (X86_TUNE_AVOID_128FMA_CHAINS): New.
	* config/i386/i386.c (ix86_option_override_internal): Added
	maybe_setting of PARAM_AVOID_FMA_MAX_BITS.

From-SVN: r256581

re PR debug/83157 (gcc.dg/guality/pr41616-1.c fail, inline instances refer to concrete instance as abstract origin)

2018-01-12  Richard Biener  <rguenther@suse.de>

	PR debug/83157
	* dwarf2out.c (gen_variable_die): Do not reset old_die for
	inline instance vars.

From-SVN: r256580

re PR target/81819 ([RX] internal compiler error: in rx_is_restricted_memory_address, at config/rx/rx.c:311)

gcc/
	PR target/81819
	* config/rx/rx.c (rx_is_restricted_memory_address):
	Handle SUBREG case.

From-SVN: r256578

It has some problems running on some 64-bit configuratiions, and the
bug it is testing for is only on 32-bit; so let's not run it elsewhere.


gcc/testsuite/
	PR target/83629
	* gcc.target/powerpc/pr83629.c: Require ilp32.

From-SVN: r256577

re PR target/80846 (auto-vectorized AVX2 horizontal sum should narrow to 128b right away, to be more efficient for Ryzen and Intel)

2018-01-12  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/80846
	* target.def (split_reduction): New target hook.
	* targhooks.c (default_split_reduction): New function.
	* targhooks.h (default_split_reduction): Declare.
	* tree-vect-loop.c (vect_create_epilog_for_reduction): If the
	target requests first reduce vectors by combining low and high
	parts.
	* tree-vect-stmts.c (vect_gen_perm_mask_any): Adjust.
	(get_vectype_for_scalar_type_and_size): Export.
	* tree-vectorizer.h (get_vectype_for_scalar_type_and_size): Declare.

	* doc/tm.texi.in (TARGET_VECTORIZE_SPLIT_REDUCTION): Document.
	* doc/tm.texi: Regenerate.

	i386/
	* config/i386/i386.c (ix86_split_reduction): Implement
	TARGET_VECTORIZE_SPLIT_REDUCTION.

	* gcc.target/i386/pr80846-1.c: New testcase.
	* gcc.target/i386/pr80846-2.c: Likewise.

From-SVN: r256576

	PR target/83368
	* config/sparc/sparc.h (PIC_OFFSET_TABLE_REGNUM): Set to INVALID_REGNUM
	in PIC mode except for TARGET_VXWORKS_RTP.
	* config/sparc/sparc.c: Include cfgrtl.h.
	(TARGET_INIT_PIC_REG): Define.
	(TARGET_USE_PSEUDO_PIC_REG): Likewise.
	(sparc_pic_register_p): New predicate.
	(sparc_legitimate_address_p): Use it.
	(sparc_legitimize_pic_address): Likewise.
	(sparc_delegitimize_address): Likewise.
	(sparc_mode_dependent_address_p): Likewise.
	(gen_load_pcrel_sym): Remove 4th parameter.
	(load_got_register): Adjust call to above.  Remove obsolete stuff.
	(sparc_expand_prologue): Do not call load_got_register here.
	(sparc_flat_expand_prologue): Likewise.
	(sparc_output_mi_thunk): Set the pic_offset_table_rtx object.
	(sparc_use_pseudo_pic_reg): New function.
	(sparc_init_pic_reg): Likewise.
	* config/sparc/sparc.md (vxworks_load_got): Set the GOT register.
	(builtin_setjmp_receiver): Enable only for TARGET_VXWORKS_RTP.

From-SVN: r256575

2018-01-12  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/
	* doc/sourcebuild.texi (Effective-Target Keywords, Other attributes):
	Add item for branch_cost.

From-SVN: r256574

	PR rtl-optimization/83565
	* rtlanal.c (nonzero_bits1): On WORD_REGISTER_OPERATIONS machines, do
	not extend the result to a larger mode for rotate operations.
	(num_sign_bit_copies1): Likewise.

From-SVN: r256572

2018-01-12  Tom de Vries  <tom@codesourcery.com>

	* g++.dg/ext/label13.C: Add dg-require-effective-target indirect_jumps.
	* g++.dg/ext/label13a.C: Same.
	* g++.dg/ext/label14.C: Same.
	* g++.dg/ext/label2.C: Same.
	* g++.dg/ext/label3.C: Same.
	* g++.dg/torture/pr42462.C: Same.
	* g++.dg/torture/pr42739.C: Same.
	* g++.dg/warn/Wunused-label-3.C: Same.

From-SVN: r256571

2018-01-12  Tom de Vries  <tom@codesourcery.com>

	* c-c++-common/dwarf2/vla1.c: Add dg-require-effective-target alloca.
	* g++.dg/Walloca1.C: Same.
	* g++.dg/cpp0x/pr70338.C: Same.
	* g++.dg/cpp1y/lambda-generic-vla1.C: Same.
	* g++.dg/cpp1y/vla10.C: Same.
	* g++.dg/cpp1y/vla2.C: Same.
	* g++.dg/cpp1y/vla6.C: Same.
	* g++.dg/cpp1y/vla8.C: Same.
	* g++.dg/debug/debug5.C: Same.
	* g++.dg/debug/debug6.C: Same.
	* g++.dg/debug/pr54828.C: Same.
	* g++.dg/diagnostic/pr70105.C: Same.
	* g++.dg/eh/cleanup5.C: Same.
	* g++.dg/eh/spbp.C: Same.
	* g++.dg/ext/tmplattr9.C: Same.
	* g++.dg/ext/vla10.C: Same.
	* g++.dg/ext/vla11.C: Same.
	* g++.dg/ext/vla12.C: Same.
	* g++.dg/ext/vla15.C: Same.
	* g++.dg/ext/vla16.C: Same.
	* g++.dg/ext/vla17.C: Same.
	* g++.dg/ext/vla3.C: Same.
	* g++.dg/ext/vla6.C: Same.
	* g++.dg/ext/vla7.C: Same.
	* g++.dg/init/array24.C: Same.
	* g++.dg/init/new47.C: Same.
	* g++.dg/init/pr55497.C: Same.
	* g++.dg/opt/pr78201.C: Same.
	* g++.dg/template/vla2.C: Same.
	* g++.dg/torture/Wsizeof-pointer-memaccess1.C: Same.
	* g++.dg/torture/Wsizeof-pointer-memaccess2.C: Same.
	* g++.dg/torture/pr62127.C: Same.
	* g++.dg/torture/pr67055.C: Same.
	* g++.dg/torture/stackalign/eh-alloca-1.C: Same.
	* g++.dg/torture/stackalign/eh-inline-2.C: Same.
	* g++.dg/torture/stackalign/eh-vararg-1.C: Same.
	* g++.dg/torture/stackalign/eh-vararg-2.C: Same.
	* g++.dg/warn/Wplacement-new-size-5.C: Same.
	* g++.dg/warn/Wsizeof-pointer-memaccess-1.C: Same.
	* g++.dg/warn/Wvla-1.C: Same.
	* g++.dg/warn/Wvla-3.C: Same.
	* g++.old-deja/g++.ext/array2.C: Same.
	* g++.old-deja/g++.ext/constructor.C: Same.
	* g++.old-deja/g++.law/builtin1.C: Same.
	* g++.old-deja/g++.other/crash12.C: Same.
	* g++.old-deja/g++.other/eh3.C: Same.
	* g++.old-deja/g++.pt/array6.C: Same.
	* g++.old-deja/g++.pt/dynarray.C: Same.

From-SVN: r256570

	* g++.dg/cpp0x/inh-ctor30.C: Allow for alternate mangled form.

From-SVN: r256569