From-SVN: r11525

From-SVN: r11524

* dbxout.c (dbxout_type):  Better "variant" handling to ignore
const/volatile but not typedef names.  Improves Feb 12 change.

From-SVN: r11523

COMPUTED.

From-SVN: r11522

From-SVN: r11521

(setjmp{,_64,_32}): New patterns.

From-SVN: r11520

an aligned union, delete check for EXPAND_SUM.

From-SVN: r11519

From-SVN: r11518

From-SVN: r11517

(flags_in_68881): New function.

From-SVN: r11516

recog.c (constrain_operands, case 'V'): Don't call offsettable_memref_p before reload has completed.

        * recog.c (constrain_operands, case 'V'): Don't call
        offsettable_memref_p before reload has completed.

From-SVN: r11515

	* h8300/h8300.h (SP_AND_G_REGS): Renamed from SP_AND_G_REG.
	(CC_DONE_CBIT): Delete.
	(CC_OVERFLOW_0,CC_OVERFLOW_UNUSABLE,CC_NO_CARRY): Define.
	* h8300/h8300.c (cond_string): Delete CC_DONE_CBIT handling.
	(notice_update_cc): Delete CC_CBIT, CC_WHOOPS.  Add CC_SET_ZN_C0.
	(restore_compare_p): New function.
	(shift_one): Use shll instead of shal so overflow bit is usable.
	Set cc_valid bits to cc_status.flags values.
	(emit_a_shift): Set cc_status.flags.
	* h8300/h8300.md (attr cc): Delete whoops,cbit.  Add set_zn_c0.
	(all patterns) Update cc attr setting.
	(tstqi,tsthi,tstsi): Delete CC_DONE_CBIT handling.
	(addhi3,subhi3): Change define_expand to define_insn.
	(branch_true,branch_false): Check if compare needs to be restored.

From-SVN: r11514

From-SVN: r11513

(jump_optimize): When handle a USE insn before an
unconditional jump, disable the optimization if the USE is the
only insn in the loop.

From-SVN: r11512

From-SVN: r11511

(simplify_comparison, case ZERO_EXTRACT): For bits big endian and no extzv,
use BITS_PER_WORD.

From-SVN: r11510

attr calcs to be more conservative.

From-SVN: r11509

(init_emit, restore_emit_status): Clear it.
(gen_sequence): Store insn in free_insn when sequence length is 1.
(make_insn_raw): Use free_insn if available and still in the rtl generation
phase.

From-SVN: r11508

From-SVN: r11507

From-SVN: r11506

From-SVN: r11505

expr.c (expand_expr, [...]): Delay putting the cleanup on the cleanup chain until after the subexpression...

	* expr.c (expand_expr, case TARGET_EXPR): Delay putting the cleanup
	on the cleanup chain until after the subexpression has been expanded.
Fixes eh44.C and eh45.C

From-SVN: r11504

Call store_field if bitpos is nonzero and target is not a MEM.

From-SVN: r11503

From-SVN: r11502

From-SVN: r11501

From-SVN: r11500

* sparc.h (TARGET_SWITCHES): Move -mlive-g0 from here,
* splet.h (SUBTARGET_SWITCHES): To here.

From-SVN: r11499

splet.h (SUBTARGET_SWITCHES): To here.

From-SVN: r11498

From-SVN: r11497

From-SVN: r11496

From-SVN: r11495

	* sparc/sparc.h (MASK_LIVE_G0,TARGET_LIVE_G0): Define.
	(TARGET_SWITCHES): Add live-g0.
	(FIRST_PSEUDO_REGISTER): Add 1 for %icc (now 101).
	(FIXED_REGISTERS,CALL_USED_REGISTERS): Update.
	(FIXED_REGISTERS): %g0 is fixed by default.
	(SPARC_{FIRST,LAST}_V9_FCC_REG): Define.
	(SPARC_{ICC,FCC}_REG): Define.
	(CONDITIONAL_REGISTER_USAGE): Don't fix %fcc0 if v8.
	(REG_CLASS_CONTENTS): Reg 0 is an int reg, reg 100 is %icc.
	(REGNO_REG_CLASS): Rewrite to use global `sparc_regno_reg_class'.
	(REG_ALLOC_ORDER,REG_LEAF_ALLOC_ORDER,LEAF_REGISTERS): Add %icc.
	(REG_CLASS_FROM_LETTER): Handle 'c' for FPCC_REGS in non-v9 case.
	(REGNO_OK_FOR_{BASE,INDEX}_P): Treat %g0 as a normal reg.
	(REG_OK_FOR_{BASE,INDEX}_P,EXTRA_CONSTRAINT): Likewise.
	(REGISTER_NAMES): Add %icc.
	(ADDITIONAL_REGISTER_NAMES): Use SPARC_ICC_REG.
	* sparc/sparc.c (leaf_reg_remap): Add %icc=100.
	(reg_or_0_operand): Don't allow 0 if TARGET_LIVE_G0.
	(fcc_reg_operand): Renamed from ccfp_reg_operand.
	Use SPARC_FCC_REG.  Don't treat reg 0 as an fcc reg.  Don't match
	modes if `mode' argument is VOIDmode.
	(icc_or_fcc_reg_operand): New function.
	(gen_compare_reg): Use SPARC_FCC_REG for v8 fp compares.
	Use SPARC_ICC_REG for int compares.
	(eligible_for_epilogue_delay): Don't allow anything if TARGET_LIVE_G0.
	Delete unnecessary test for %g0.
	(emit_move_sequence): Don't emit (set (mem) (const_int 0)) if
	TARGET_LIVE_G0.
	(output_scc_insn): Label moved to operand 3.  Condition code reg
	moved to operand 2.
	(sparc_mode_class): Enum C_MODE renamed to CC_MODE.
	(hard_32bit_mode_classes): Set reg 0 to S_MODES.  Add entry for %icc.
	(hard_64bit_mode_classes): Set reg 0 to D_MODES.  Add entry for %icc.
	(sparc_regno_reg_class): New global.
	(sparc_init_modes): Initialize it.
	(output_cbranch): Delete fp_cond_reg argument.
	(print_operand, MEM op): Don't print "%g0+" if TARGET_SPARCLET.
	(sparc_flat_eligible_for_epilogue_delay): Don't allow anything if
	TARGET_LIVE_G0.
	* sparc/sparc.md (live_g0): New attribute.
	(*): Integer condition code register is now reg 100.
	Use SPARC_ICC_REG instead of hardcoding reg 100 where possible.
	Non-v9 floating point condition code register is now reg 96.
	(*cmp{sf,df,tf}_{fpe,fp}_sp{32,64}): Combine v9/non-v9 cases.
	(*{normal,inverted}_{,fp,fpe}_branch): Update call to output_cbranch.
	(*mov{qi,hi,si}_insn): Don't use if TARGET_LIVE_G0.
	(*mov{qi,hi,si}_insn_liveg0): New patterns.
	(*mov{si,di,sf,df,tf}_ccfp{,e}_sp64): ccfp_reg_operand renamed to
	fcc_reg_operand.
	(*negdi2_sp32,negsi2,one_cmplsi2,ffssi2): Ensure %%g0 is 0 if
	TARGET_LIVE_G0.
	(*one_cmpldi2_sp32): Move operand 1 to rs1 and use 0 as rs2.
	(patterns that use %g0 in rs2): Use 0 immediate value instead.
	(patterns that read %g0): Don't use if TARGET_LIVE_G0.

From-SVN: r11494

From-SVN: r11493

(va_arg): Add little-endian SH3E support.  Fix big-endian version
to work for arguments smaller than the word size.

From-SVN: r11492

        * lib2funcs.asm: Remove entry/exit routines.  Move them into...
        * ee.asm: New file.  Entry/exit code.
        * ee_fp.asm: New file.  Entry/exit code with frame pointer.
        * t-pa: Corresponding changes.
        * t-pro: Corresponding changes.

From-SVN: r11491

From-SVN: r11490

 
        * pa.c: Fix misc small typos/thinkos in recent changes.

From-SVN: r11489

From-SVN: r11488

From-SVN: r11487

From-SVN: r11486