This patch makes the SVE unary, binary and ternary FP unspecs
take a new "GP strictness" operand that indicates whether the
predicate has to be taken literally, or whether it is valid to
make extra lanes active (up to and including using a PTRUE).

This again is laying the groundwork for the ACLE patterns,
in which the value can depend on the FP command-line flags.

At the moment it's only needed for addition, subtraction and
multiplication, which have unpredicated forms that can only
be used when operating on all lanes is safe.  But in future
it might be useful for optimising predicate usage.

The strict mode requires extra alternatives for addition,
subtraction and multiplication, but I've left those for the
main ACLE patch.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>
	    Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

gcc/
	* config/aarch64/aarch64.md (SVE_RELAXED_GP, SVE_STRICT_GP): New
	constants.
	* config/aarch64/predicates.md (aarch64_sve_gp_strictness): New
	predicate.
	* config/aarch64/aarch64-protos.h (aarch64_sve_pred_dominates_p):
	Declare.
	* config/aarch64/aarch64.c (aarch64_sve_pred_dominates_p): New
	function.
	* config/aarch64/aarch64-sve.md: Add a block comment about the
	handling of predicated FP operations.
	(<SVE_COND_FP_UNARY:optab><SVE_F:mode>2, add<SVE_F:mode>3)
	(sub<SVE_F:mode>3, mul<SVE_F:mode>3, div<SVE_F:mode>3)
	(<SVE_COND_FP_MAXMIN_PUBLIC:optab><SVE_F:mode>3)
	(<SVE_COND_FP_MAXMIN_PUBLIC:maxmin_uns><SVE_F:mode>3)
	(<SVE_COND_FP_TERNARY:optab><SVE_F:mode>4): Add an SVE_RELAXED_GP
	operand.
	(cond_<SVE_COND_FP_BINARY:optab><SVE_F:mode>)
	(cond_<SVE_COND_FP_TERNARY:optab><SVE_F:mode>): Add an SVE_STRICT_GP
	operand.
	(*<SVE_COND_FP_UNARY:optab><SVE_F:mode>2)
	(*cond_<SVE_COND_FP_BINARY:optab><SVE_F:mode>_2)
	(*cond_<SVE_COND_FP_BINARY:optab><SVE_F:mode>_3)
	(*cond_<SVE_COND_FP_BINARY:optab><SVE_F:mode>_any)
	(*fabd<SVE_F:mode>3, *div<SVE_F:mode>3)
	(*<SVE_COND_FP_MAXMIN_PUBLIC:optab><SVE_F:mode>3)
	(*<SVE_COND_FP_TERNARY:optab><SVE_F:mode>4)
	(*cond_<SVE_COND_FP_TERNARY:optab><SVE_F:mode>_2)
	(*cond_<SVE_COND_FP_TERNARY:optab><SVE_F:mode>_4)
	(*cond_<SVE_COND_FP_TERNARY:optab><SVE_F:mode>_any): Match the
	strictness operands.  Use aarch64_sve_pred_dominates_p to check
	whether the predicate on the conditional operation is suitable
	for merging.  Split patterns into the canonical equal-predicate form.
	(*add<SVE_F:mode>3, *sub<SVE_F:mode>3, *mul<SVE_F:mode>3): Likewise.
	Restrict the unpredicated alternatives to SVE_RELAXED_GP.

Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org>

From-SVN: r274418

Another patch in the series to make the SVE FP patterns use unspecs,
so that they can accurately describe cases in which the predicate
isn't a PTRUE.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>
	    Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

gcc/
	* config/aarch64/aarch64-sve.md (add<mode>3, *add<mode>3)
	(sub<mode>3, *sub<mode>3, *fabd<mode>3, mul<mode>3, *mul<mode>3)
	(div<mode>3, *div<mode>3): Use SVE_COND_FP_* unspecs instead of
	rtx codes.
	(cond_<optab><mode>, *cond_<optab><mode>_2, *cond_<optab><mode>_3)
	(*cond_<optab><mode>_any): Add the predicate to the SVE_COND_FP_*
	unspecs.

Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org>

From-SVN: r274417

This patch generalises the SVE BIC pattern so that it doesn't
rely on REG_EQUAL notes.  The danger with relying on the notes
is that an optimisation could for example replace the original
(not ...) note with an (unspec ... UNSPEC_MERGE_PTRUE) in which
the predicate is a constant.  That's a legitimate change and
could even be useful in some situations.

The patch also makes the operand order match the SVE operand order in
both the vector and predicate BIC patterns, which makes things easier
for the ACLE.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>
	    Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

gcc/
	* config/aarch64/aarch64-sve.md (bic<mode>3): Rename to...
	(*bic<SVE_I:mode>3): ...this.  Match the form that an SVE inverse
	actually has, rather than relying on REG_EQUAL notes.
	Make the insn operand order match the SVE operand order.
	(*<nlogical><PRED_ALL:mode>3): Make the insn operand order match
	the SVE operand order.

Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org>

From-SVN: r274416

This patch makes sure that we build all SVE predicate constants as
VNx16BI before RA, to encourage similar constants to be reused
between modes.  This is also useful for the ACLE, where the single
predicate type svbool_t is always a VNx16BI.

Also, and again to encourage reuse, the patch makes us use a .B PTRUE
for all ptrue-predicated operations, rather than (for example) using
a .S PTRUE for 32-bit operations and a .D PTRUE for 64-bit operations.

The only current case in which a .H, .S or .D operation needs to be
predicated by a "strict" .H/.S/.D PTRUE is the PTEST in a conditional
branch, which an earlier patch fixed to use an appropriate VNx16BI
constant.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64.c (aarch64_target_reg): New function.
	(aarch64_emit_set_immediate): Likewise.
	(aarch64_ptrue_reg): Build a VNx16BI constant and then bitcast it.
	(aarch64_pfalse_reg): Likewise.
	(aarch64_convert_sve_data_to_pred): New function.
	(aarch64_sve_move_pred_via_while): Take an optional target register
	and the required register mode.
	(aarch64_expand_sve_const_pred_1): New function.
	(aarch64_expand_sve_const_pred): Likewise.
	(aarch64_expand_mov_immediate): Build an all-true predicate
	if the significant bits of the immediate are all true.  Use
	aarch64_expand_sve_const_pred for all compile-time predicate constants.
	(aarch64_mov_operand_p): Force predicate constants to be VNx16BI
	before register allocation.
	* config/aarch64/aarch64-sve.md (*vec_duplicate<mode>_reg): Use
	a VNx16BI PTRUE when splitting the memory alternative.
	(vec_duplicate<mode>): Update accordingly.
	(*pred_cmp<cmp_op><mode>): Rename to...
	(@aarch64_pred_cmp<cmp_op><mode>): ...this.

gcc/testsuite/
	* gcc.target/aarch64/sve/spill_4.c: Expect all ptrues to be .Bs.
	* gcc.target/aarch64/sve/single_1.c: Likewise.
	* gcc.target/aarch64/sve/single_2.c: Likewise.
	* gcc.target/aarch64/sve/single_3.c: Likewise.
	* gcc.target/aarch64/sve/single_4.c: Likewise.

From-SVN: r274415

This patch reworks the rtl representation of the SVE PTEST operation
so that:

- the governing predicate is always VNx16BI (and so all bits are defined)

- it is still possible to pattern-match the governing predicate in the
  mode that it had previously

- a new hint operand says whether the governing predicate is known to be
  all true for the element size of interest, rather than this being part
  of the unspec name.

These changes make it easier to handle more flag-setting instructions
as part of the ACLE work.

See the comment in aarch64-sve.md for more details.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64-protos.h (aarch64_ptrue_all): Declare.
	* config/aarch64/aarch64.c (aarch64_ptrue_all): New function.
	* config/aarch64/aarch64.md (UNSPEC_PTEST_PTRUE): Delete.
	(UNSPEC_PTEST): New unspec.
	(SVE_MAYBE_NOT_PTRUE, SVE_KNOWN_PTRUE): New constants.
	* config/aarch64/iterators.md (data_bytes): New mode attribute.
	* config/aarch64/predicates.md (aarch64_sve_ptrue_flag): New predicate.
	* config/aarch64/aarch64-sve.md: Add a new section describing the
	handling of UNSPEC_PTEST.
	(pred_<LOGICAL:optab><PRED_ALL:mode>3): Rename to...
	(@aarch64_pred_<LOGICAL:optab><PRED_ALL:mode>_z): ...this.
	(ptest_ptrue<mode>): Replace with...
	(aarch64_ptest<mode>): ...this new pattern.
	(cbranch<mode>4): Update after above changes.
	(*<LOGICAL:optab><PRED_ALL:mode>3_cc): Use UNSPEC_PTEST instead of
	UNSPEC_PTEST_PTRUE.
	(*cmp<SVE_INT_CMP:cmp_op><SVE_I:mode>_cc): Likewise.
	(*cmp<SVE_INT_CMP:cmp_op><SVE_I:mode>_ptest): Likewise.
	(*while_ult<GPI:mode><PRED_ALL:mode>_cc): Likewise.

From-SVN: r274414

2019-08-13  Steven G. Kargl  <kargl@gcc.gnu.org>

	PR fortran/87991
	* resolve.c (check_data_variable): data-stmt-object with pointer
	attribute requires a data-stmt-value with the target attribute.
 
2019-08-13  Steven G. Kargl  <kargl@gcc.gnu.org>

	PR fortran/87991
	* gfortran.dg/pr87991.f90: New test.

From-SVN: r274412

In LTO mode, if static library and dynamic library contains same
function and both libraries are passed as arguments, linker will link
the function in dynamic library no matter the sequence.  This patch
will output LTO symbol node as UNDEF if BUILT_IN_NORMAL function FNDECL
is a math function, then the function in static library will be linked
first if its sequence is ahead of the dynamic library.

gcc/ChangeLog

2019-08-14  Xiong Hu Luo  <luoxhu@linux.ibm.com>

	PR lto/91287
	* builtins.c (builtin_with_linkage_p): New function.
	* builtins.h (builtin_with_linkage_p): New function.
	* symtab.c (write_symbol): Remove redundant assert.
	* lto-streamer-out.c (symtab_node::output_to_lto_symbol_table_p):
	Remove FIXME and use builtin_with_linkage_p.

From-SVN: r274411

From-SVN: r274410

We were shoe-horning all built-in enumerations (including frontend
and target-specific ones) into a field of type built_in_function.  This
was accessed as either an lvalue or an rvalue using DECL_FUNCTION_CODE.

The obvious danger with this (as was noted by several ??? comments)
is that the ranges have nothing to do with each other, and targets can
easily have more built-in functions than generic code.  But my patch to
make the field bigger was the straw that finally made the problem visible.

This patch therefore:

- replaces the field with a plain unsigned int

- turns DECL_FUNCTION_CODE into an rvalue-only accessor that checks
  that the function really is BUILT_IN_NORMAL

- adds corresponding DECL_MD_FUNCTION_CODE and DECL_FE_FUNCTION_CODE
  accessors for BUILT_IN_MD and BUILT_IN_FRONTEND respectively

- adds DECL_UNCHECKED_FUNCTION_CODE for places that need to access the
  underlying field (should be low-level code only)

- adds new helpers for setting the built-in class and function code

- makes DECL_BUILT_IN_CLASS an rvalue-only accessor too, since all
  assignments should go through the new helpers

2019-08-13  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	PR middle-end/91421
	* tree-core.h (function_decl::function_code): Change type to
	unsigned int.
	* tree.h (DECL_FUNCTION_CODE): Rename old definition to...
	(DECL_UNCHECKED_FUNCTION_CODE): ...this.
	(DECL_BUILT_IN_CLASS): Make an rvalue macro only.
	(DECL_FUNCTION_CODE): New function.  Assert that the built-in class
	is BUILT_IN_NORMAL.
	(DECL_MD_FUNCTION_CODE, DECL_FE_FUNCTION_CODE): New functions.
	(set_decl_built_in_function, copy_decl_built_in_function): Likewise.
	(fndecl_built_in_p): Change the type of the "name" argument to
	unsigned int.
	* builtins.c (expand_builtin): Move DECL_FUNCTION_CODE use
	after check for DECL_BUILT_IN_CLASS.
	* cgraphclones.c (build_function_decl_skip_args): Use
	set_decl_built_in_function.
	* ipa-param-manipulation.c (ipa_modify_formal_parameters): Likewise.
	* ipa-split.c (split_function): Likewise.
	* langhooks.c (add_builtin_function_common): Likewise.
	* omp-simd-clone.c (simd_clone_create): Likewise.
	* tree-streamer-in.c (unpack_ts_function_decl_value_fields): Likewise.
	* config/darwin.c (darwin_init_cfstring_builtins): Likewise.
	(darwin_fold_builtin): Use DECL_MD_FUNCTION_CODE instead of
	DECL_FUNCTION_CODE.
	* fold-const.c (operand_equal_p): Compare DECL_UNCHECKED_FUNCTION_CODE
	instead of DECL_FUNCTION_CODE.
	* lto-streamer-out.c (hash_tree): Use DECL_UNCHECKED_FUNCTION_CODE
	instead of DECL_FUNCTION_CODE.
	* tree-streamer-out.c (pack_ts_function_decl_value_fields): Likewise.
	* print-tree.c (print_node): Use DECL_MD_FUNCTION_CODE when
	printing DECL_BUILT_IN_MD.  Handle DECL_BUILT_IN_FRONTEND.
	* config/aarch64/aarch64-builtins.c (aarch64_expand_builtin)
	(aarch64_fold_builtin, aarch64_gimple_fold_builtin): Use
	DECL_MD_FUNCTION_CODE instead of DECL_FUNCTION_CODE.
	* config/aarch64/aarch64.c (aarch64_builtin_reciprocal): Likewise.
	* config/alpha/alpha.c (alpha_expand_builtin, alpha_fold_builtin):
	(alpha_gimple_fold_builtin): Likewise.
	* config/arc/arc.c (arc_expand_builtin): Likewise.
	* config/arm/arm-builtins.c (arm_expand_builtin): Likewise.
	* config/avr/avr-c.c (avr_resolve_overloaded_builtin): Likewise.
	* config/avr/avr.c (avr_expand_builtin, avr_fold_builtin): Likewise.
	* config/bfin/bfin.c (bfin_expand_builtin): Likewise.
	* config/c6x/c6x.c (c6x_expand_builtin): Likewise.
	* config/frv/frv.c (frv_expand_builtin): Likewise.
	* config/gcn/gcn.c (gcn_expand_builtin_1): Likewise.
	(gcn_expand_builtin): Likewise.
	* config/i386/i386-builtins.c (ix86_builtin_reciprocal): Likewise.
	(fold_builtin_cpu): Likewise.
	* config/i386/i386-expand.c (ix86_expand_builtin): Likewise.
	* config/i386/i386.c (ix86_fold_builtin): Likewise.
	(ix86_gimple_fold_builtin): Likewise.
	* config/ia64/ia64.c (ia64_fold_builtin): Likewise.
	(ia64_expand_builtin): Likewise.
	* config/iq2000/iq2000.c (iq2000_expand_builtin): Likewise.
	* config/mips/mips.c (mips_expand_builtin): Likewise.
	* config/msp430/msp430.c (msp430_expand_builtin): Likewise.
	* config/nds32/nds32-intrinsic.c (nds32_expand_builtin_impl): Likewise.
	* config/nios2/nios2.c (nios2_expand_builtin): Likewise.
	* config/nvptx/nvptx.c (nvptx_expand_builtin): Likewise.
	* config/pa/pa.c (pa_expand_builtin): Likewise.
	* config/pru/pru.c (pru_expand_builtin): Likewise.
	* config/riscv/riscv-builtins.c (riscv_expand_builtin): Likewise.
	* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
	Likewise.
	* config/rs6000/rs6000-call.c (htm_expand_builtin): Likewise.
	(altivec_expand_dst_builtin, altivec_expand_builtin): Likewise.
	(rs6000_gimple_fold_builtin, rs6000_expand_builtin): Likewise.
	* config/rs6000/rs6000.c (rs6000_builtin_md_vectorized_function)
	(rs6000_builtin_reciprocal): Likewise.
	* config/rx/rx.c (rx_expand_builtin): Likewise.
	* config/s390/s390-c.c (s390_resolve_overloaded_builtin): Likewise.
	* config/s390/s390.c (s390_expand_builtin): Likewise.
	* config/sh/sh.c (sh_expand_builtin): Likewise.
	* config/sparc/sparc.c (sparc_expand_builtin): Likewise.
	(sparc_fold_builtin): Likewise.
	* config/spu/spu-c.c (spu_resolve_overloaded_builtin): Likewise.
	* config/spu/spu.c (spu_expand_builtin): Likewise.
	* config/stormy16/stormy16.c (xstormy16_expand_builtin): Likewise.
	* config/tilegx/tilegx.c (tilegx_expand_builtin): Likewise.
	* config/tilepro/tilepro.c (tilepro_expand_builtin): Likewise.
	* config/xtensa/xtensa.c (xtensa_fold_builtin): Likewise.
	(xtensa_expand_builtin): Likewise.

gcc/ada/
	PR middle-end/91421
	* gcc-interface/trans.c (gigi): Call set_decl_buillt_in_function.
	(Call_to_gnu): Use DECL_FE_FUNCTION_CODE instead of DECL_FUNCTION_CODE.

gcc/c/
	PR middle-end/91421
	* c-decl.c (merge_decls): Use copy_decl_built_in_function.

gcc/c-family/
	PR middle-end/91421
	* c-common.c (resolve_overloaded_builtin): Use
	copy_decl_built_in_function.

gcc/cp/
	PR middle-end/91421
	* decl.c (duplicate_decls):  Use copy_decl_built_in_function.
	* pt.c (declare_integer_pack): Use set_decl_built_in_function.

gcc/d/
	PR middle-end/91421
	* intrinsics.cc (maybe_set_intrinsic): Use set_decl_built_in_function.

gcc/jit/
	PR middle-end/91421
	* jit-playback.c (new_function): Use set_decl_built_in_function.

gcc/lto/
	PR middle-end/91421
	* lto-common.c (compare_tree_sccs_1): Use DECL_UNCHECKED_FUNCTION_CODE
	instead of DECL_FUNCTION_CODE.
	* lto-symtab.c (lto_symtab_merge_p): Likewise.

From-SVN: r274404

This patch protects various uses of DECL_FUNCTION_CODE that didn't
obviously check for BUILT_IN_NORMAL first (either directly or in callers).
They could therefore trigger for functions that either aren't built-ins
or are a different kind of built-in.

Also, the patch removes a redundant GIMPLE_CALL check from
optimize_stdarg_builtin, since it gave the impression that the stmt
was less well checked than it actually is.

2019-08-13  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	PR middle-end/91421
	* attribs.c (decl_attributes): Check the DECL_BUILT_IN_CLASS
	before the DECL_FUNCTION_CODE.
	* calls.c (maybe_warn_alloc_args_overflow): Use fndecl_built_in_p
	to check for a BUILT_IN_ALLOCA call.
	* ipa-cp.c (ipa_get_indirect_edge_target_1): Likewise for
	BUILT_IN_UNREACHABLE.  Don't check for a FUNCTION_TYPE.
	* ipa-devirt.c (possible_polymorphic_call_target_p): Likewise.
	* ipa-prop.c (try_make_edge_direct_virtual_call): Likewise.
	* gimple-ssa-isolate-paths.c (is_addr_local): Check specifically
	for BUILT_IN_NORMAL functions.
	* trans-mem.c (expand_block_edges): Use gimple_call_builtin_p to
	test for BUILT_IN_TM_ABORT.
	* tree-ssa-ccp.c (optimize_stack_restore): Use fndecl_built_in_p
	to check for a BUILT_IN_STACK_RESTORE call.
	(optimize_stdarg_builtin): Remove redundant check for GIMPLE_CALL.
	* tree-ssa-threadedge.c
	(record_temporary_equivalences_from_stmts_at_dest): Check for a
	BUILT_IN_NORMAL decl before checking its DECL_FUNCTION_CODE.
	* tree-vect-patterns.c (vect_recog_pow_pattern): Use a positive
	test for a BUILT_IN_NORMAL call instead of a negative test for
	an internal function call.

gcc/c/
	PR middle-end/91421
	* c-decl.c (header_for_builtin_fn): Take a FUNCTION_DECL instead
	of a built_in_function.
	(diagnose_mismatched_decls, implicitly_declare): Update accordingly.

From-SVN: r274403

This patch is a combination of two changes that have to be
committed as a single unit:

(1) Try to fold IFN_WHILE_ULTs with constant arguments to a VECTOR_CST
    (which is always possible for fixed-length vectors but is not
    necessarily so for variable-length vectors)

(2) Make the SVE port recognise constants that map to PTRUE VLn,
    which includes those generated by the new fold.

(2) can't be tested without (1) and (1) would be a significant
pessimisation without (2).

The target-specific parts also start moving towards doing predicate
manipulation in a canonical VNx16BImode form, using rtx_vector_builders.

2019-08-13  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* tree.h (build_vector_a_then_b): Declare.
	* tree.c (build_vector_a_then_b): New function.
	* fold-const-call.c (fold_while_ult): Likewise.
	(fold_const_call): Use it to handle IFN_WHILE_ULT.
	* config/aarch64/aarch64-protos.h (AARCH64_FOR_SVPATTERN): New macro.
	(aarch64_svpattern): New enum.
	* config/aarch64/aarch64-sve.md (mov<PRED_ALL:mode>): Pass
	constants through aarch64_expand_mov_immediate.
	(*aarch64_sve_mov<PRED_ALL:mode>): Use aarch64_mov_operand rather
	than general_operand as the predicate for operand 1.
	(while_ult<GPI:mode><PRED_ALL:mode>): Add a '@' marker.
	* config/aarch64/aarch64.c (simd_immediate_info::PTRUE): New
	insn_type.
	(simd_immediate_info::simd_immediate_info): New overload that
	takes a scalar_int_mode and an svpattern.
	(simd_immediate_info::u): Add a "pattern" field.
	(svpattern_token): New function.
	(aarch64_get_sve_pred_bits, aarch64_widest_sve_pred_elt_size)
	(aarch64_partial_ptrue_length, aarch64_svpattern_for_vl)
	(aarch64_sve_move_pred_via_while): New functions.
	(aarch64_expand_mov_immediate): Try using
	aarch64_sve_move_pred_via_while for predicates that contain N ones
	followed by M zeros but that do not correspond to a VLnnn pattern.
	(aarch64_sve_pred_valid_immediate): New function.
	(aarch64_simd_valid_immediate): Use it instead of dealing directly
	with PTRUE and PFALSE.
	(aarch64_output_sve_mov_immediate): Handle new simd_immediate_info
	forms.

gcc/testsuite/
	* gcc.target/aarch64/sve/spill_2.c: Increase iteration counts
	beyond the range of a PTRUE.
	* gcc.target/aarch64/sve/while_6.c: New test.
	* gcc.target/aarch64/sve/while_7.c: Likewise.
	* gcc.target/aarch64/sve/while_8.c: Likewise.
	* gcc.target/aarch64/sve/while_9.c: Likewise.
	* gcc.target/aarch64/sve/while_10.c: Likewise.

From-SVN: r274402

2019-08-13  Steven G. Kargl  <kargl@gcc.gnu.org> 

	PR fortran/88072
	* gfortran.dg/unlimited_polymorphic_28.f90: Fix error message.  Left
	out of previous commit!

From-SVN: r274400

2019-08-13  Steven G. Kargl  <kargl@gcc.gnu.org>

	PR fortran/88072
	* misc.c (gfc_typename): Do not point to something that ought not to 
	be pointed at.

2019-08-13  Steven G. Kargl  <kargl@gcc.gnu.org>

	PR fortran/88072
	* gfortran.dg/pr88072.f90: New test.
	* gfortran.dg/unlimited_polymorphic_28.f90: Fix error message.

From-SVN: r274399

So we can use a single flag for both, and rename this now, before a confusing
name gets into the wild.

gcc/

2019-08-13 Iain Sandoe <iain@sandoe.co.uk>

	* config/darwin.c (machopic_indirect_call_target): Rename symbol stub
	flag.
	(darwin_override_options): Likewise.
	* config/darwin.h: Likewise.
	* config/darwin.opt: Likewise.
	* config/i386/i386.c (output_pic_addr_const): Likewise.
	* config/rs6000/darwin.h: Likewise.
	* config/rs6000/rs6000.c (rs6000_call_darwin_1): Likewise.
	* config/i386/darwin.h (TARGET_MACHO_PICSYM_STUBS): Rename to ...
	... this TARGET_MACHO_SYMBOL_STUBS.
	(FUNCTION_PROFILER):Likewise.
	* config/i386/i386.h: Likewise.

gcc/testsuite/

2019-08-13  Iain Sandoe  <iain@sandoe.co.uk>

	* obj-c++.dg/stubify-1.mm: Rename symbol stub option.
	* obj-c++.dg/stubify-2.mm: Likewise.
	* objc.dg/stubify-1.m: Likewise.
	* objc.dg/stubify-2.m: Likewise.

From-SVN: r274397

2013-08-13  Thomas Koenig  <tkoenig@gcc.gnu.org>

	PR fortran/90563
	* gfortran.dg/do_subsript_5.f90: Correct test.

From-SVN: r274396

2013-08-13  Thomas Koenig  <tkoenig@gcc.gnu.org>

	PR fortran/90563
	* frontend-passes.c (insert_index): Suppress errors while
	simplifying the resulting expression.

2013-08-13  Thomas Koenig  <tkoenig@gcc.gnu.org>

	PR fortran/90563
	* gfortran.dg/do_subsript_5.f90: New test.

From-SVN: r274394

2019-08-13  Steven G. Kargl  <kargl@gcc.gnu.org>

	PR fortran/89647
	resolve.c (resolve_typebound_procedure): Allow host associated 
	procedure to be a binding target.  While here, wrap long line.

2019-08-13  Steven G. Kargl  <kargl@gcc.gnu.org>

	PR fortran/89647
	* gfortran.dg/pr89647.f90: New test.

From-SVN: r274393

	* config/i386/i386.md (ix86_expand_vector_extract) <case E_V2SImode>:
	Use vec_extr path for TARGET_MMX_WITH_SSE && TARGET_SSE4_1.
	<case E_V8QImode>: Ditto.
	* config/i386/mmx.md (*mmx_pextrw_zext): Rename from mmx_pextrw.
	Use SWI48 mode iterator.  Use %k to output operand 0.
	(*mmx_pextrw): New insn pattern.
	(*mmx_pextrb): Ditto.
	(*mmx_pextrb_zext): Ditto.

From-SVN: r274389

2019-08-13  Steven G. Kargl  <kargl@gcc.gnu.org>

	PR fortran/87993
	* expr.c (gfc_simplify_expr): Simplifcation of an array with a kind
	type inquiry suffix yields a constant expression.

2019-08-13  Steven G. Kargl  <kargl@gcc.gnu.org>

	PR fortran/87993
	* gfortran.dg/pr87993.f90: New test.

From-SVN: r274388

	* target.def (libc_has_function, libc_has_fast_function): Improve
	documentation strings.
	* doc/tm.texi: Regenerate.

From-SVN: r274387

Fix a bug where linking with -fvtable-verify  and
-static causes the linker to complain about multiple definitions of
things in the vtv_end*.o files (once from the .o file and once from
libvtv.a).

2019-08-12  Caroline Tice  <cmtice@google.com>

        PR other/91396
        * config/gnu-user.h (GNU_USER_TARGET_ENDFILE_SPEC): Only add the
        vtv_end.o or vtv_end_preinit.o files if !static.

From-SVN: r274386

gcc/c-family/ChangeLog:

	PR c/80619
	* c-format.c (printf_length_specs): Set FMT_LEN_w for "w".
	(asm_fprintf_length_spec): Same.
	* c-format.h (format_lengths): Add FMT_LEN_w.

gcc/testsuite/ChangeLog:

	PR c/80619
	* gcc.dg/format/pr80619.c: New test.

From-SVN: r274385

	* test_summary: Do not escape "=".

From-SVN: r274384

2019-08-13  Thomas Koenig  <tkoenig@gcc.gnu.org>

	PR fortran/90561
	* trans.h (gfc_evaluate_now_function_scope): New function.
	* trans.c (gfc_evaluate_now_function_scope): New function.
	* trans-expr.c (gfc_trans_assignment): Use it.

2019-08-13  Thomas Koenig  <tkoenig@gcc.gnu.org>

	PR fortran/90561
	* gfortran.dg/deferred_character_34.f90: New test.

From-SVN: r274383

	* call.c (null_ptr_cst_p): Update quote from the standard.
	* decl.c (check_default_argument): Don't return nullptr when the arg
	has side-effects.

	* g++.dg/cpp0x/nullptr42.C: New test.

From-SVN: r274382

From-SVN: r274381

From-SVN: r274380

So it appears next to the prototype of tablejump_p, matching
the definition placement in rtlanal.c.

From-SVN: r274378

	* rtlanal.c (tablejump_casesi_pattern): New function, to
	determine if a tablejump insn is a casesi dispatcher. Extracted
	from patch_jump_insn.
	* rtl.h (tablejump_casesi_pattern): Declare.
	* cfgrtl.c (patch_jump_insn): Use it.
	* dwarf2cfi.c (create_trace_edges): Use it.

testsuite/

	* gnat.dg/casesi.ad[bs], test_casesi.adb: New test.

From-SVN: r274377

PR81800 is about the lrint inline giving spurious FE_INEXACT exceptions.
The previous change for PR81800 didn't fix this: when lrint is disabled
in the backend, the midend will simply use llrint.  This actually makes
things worse since llrint now also ignores FE_INVALID exceptions!
The fix is to disable lrint/llrint on double if the size of a long is
smaller (ie. ilp32).

    gcc/
	PR target/81800
	* gcc/config/aarch64/aarch64.md (lrint): Disable lrint pattern if GPF
	operand is larger than a long int.

    testsuite/
	PR target/81800
	* gcc.target/aarch64/no-inline-lrint_3.c: New test.

From-SVN: r274376

If there's no SVE instruction to load a given constant directly, this
patch instead tries to use an Advanced SIMD constant move and then
duplicates the constant to fill an SVE vector.  The main use of this
is to support constants in which each byte is in { 0, 0xff }.

Also, the patch prefers a simple integer move followed by a duplicate
over a load from memory, like we already do for Advanced SIMD.  This is
a useful option to have and would be easy to turn off via a tuning
parameter if necessary.

The patch also extends the handling of wide LD1Rs to big endian,
whereas previously we punted to a full LD1RQ.

2019-08-13  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* machmode.h (opt_mode::else_mode): New function.
	(opt_mode::else_blk): Use it.
	* config/aarch64/aarch64-protos.h (aarch64_vq_mode): Declare.
	(aarch64_full_sve_mode, aarch64_sve_ld1rq_operand_p): Likewise.
	(aarch64_gen_stepped_int_parallel): Likewise.
	(aarch64_stepped_int_parallel_p): Likewise.
	(aarch64_expand_mov_immediate): Remove the optional gen_vec_duplicate
	argument.
	* config/aarch64/aarch64.c
	(aarch64_expand_sve_widened_duplicate): Delete.
	(aarch64_expand_sve_dupq, aarch64_expand_sve_ld1rq): New functions.
	(aarch64_expand_sve_const_vector): Rewrite to handle more cases.
	(aarch64_expand_mov_immediate): Remove the optional gen_vec_duplicate
	argument.  Use early returns in the !CONST_INT_P handling.
	Pass all SVE data vectors to aarch64_expand_sve_const_vector rather
	than handling some inline.
	(aarch64_full_sve_mode, aarch64_vq_mode): New functions, split out
	from...
	(aarch64_simd_container_mode): ...here.
	(aarch64_gen_stepped_int_parallel, aarch64_stepped_int_parallel_p)
	(aarch64_sve_ld1rq_operand_p): New functions.
	* config/aarch64/predicates.md (descending_int_parallel)
	(aarch64_sve_ld1rq_operand): New predicates.
	* config/aarch64/constraints.md (UtQ): New constraint.
	* config/aarch64/aarch64.md (UNSPEC_REINTERPRET): New unspec.
	* config/aarch64/aarch64-sve.md (mov<SVE_ALL:mode>): Remove the
	gen_vec_duplicate from call to aarch64_expand_mov_immediate.
	(@aarch64_sve_reinterpret<mode>): New expander.
	(*aarch64_sve_reinterpret<mode>): New pattern.
	(@aarch64_vec_duplicate_vq<mode>_le): New pattern.
	(@aarch64_vec_duplicate_vq<mode>_be): Likewise.
	(*sve_ld1rq<Vesize>): Replace with...
	(@aarch64_sve_ld1rq<mode>): ...this new pattern.

gcc/testsuite/
	* gcc.target/aarch64/sve/init_2.c: Expect ld1rd to be used
	instead of a full vector load.
	* gcc.target/aarch64/sve/init_4.c: Likewise.
	* gcc.target/aarch64/sve/ld1r_2.c: Remove constants that no longer
	need to be loaded from memory.
	* gcc.target/aarch64/sve/slp_2.c: Expect the same output for
	big and little endian.
	* gcc.target/aarch64/sve/slp_3.c: Likewise.  Expect 3 of the
	doubles to be moved via integer registers rather than loaded
	from memory.
	* gcc.target/aarch64/sve/slp_4.c: Likewise but for 4 doubles.
	* gcc.target/aarch64/sve/spill_4.c: Expect 16-bit constants to be
	loaded via an integer register rather than from memory.
	* gcc.target/aarch64/sve/const_1.c: New test.
	* gcc.target/aarch64/sve/const_2.c: Likewise.
	* gcc.target/aarch64/sve/const_3.c: Likewise.

From-SVN: r274375

With -mcpu=generic the function alignment is currently 8, however almost all
supported cores prefer 16 or higher, so increase the default to 16:12.
This gives ~0.2% performance increase on SPECINT2017, while codesize is 0.12%
larger.

    gcc/
	* config/aarch64/aarch64.c (generic_tunings): Set function alignment to
	16:12.

From-SVN: r274374

gcc/ChangeLog:

2019-08-13  Jozef Lawrynowicz  <jozef.l@mittosystems.com>

	* config/msp430/driver-msp430.c (msp430_set_driver_var): New.
	* config/msp430/msp430-devices.c (canonicalize_path_dirsep): New.
	(msp430_check_path_for_devices): New.
	(parse_devices_csv_1): New.
	(parse_devices_csv): New.
	(msp430_extract_mcu_data): Try to find devices.csv and search for the
	MCU data in devices.csv before using the hard-coded data.
	Warn if devices.csv isn't found and the MCU wasn't found in the
	hard-coded data either.
	* config/msp430/msp430.h (DRIVER_SELF_SPECS): Call
	msp430_set_driver_var for -mno-warn-devices-csv and -mdevices-csv-loc.
	Search for devices.csv on -I and -L paths.
	(EXTRA_SPEC_FUNCTIONS): Add msp430_check_path_for_devices and
	msp430_set_driver_var.
	* config/msp430/msp430.opt: Add -mwarn-devices-csv and
	-mdevices-csv-loc=.
	* doc/invoke.texi (-mmcu): Document that -I and -L paths are
	searched for devices.csv.
	(mwarn-devices-csv): Document option.

gcc/testsuite/ChangeLog:

2019-08-13  Jozef Lawrynowicz  <jozef.l@mittosystems.com>

	* gcc.target/msp430/msp430.exp (msp430_device_permutations_runtest):
	Handle csv-* and bad-devices-* tests.
	* gcc.target/msp430/devices/README: Document how bad-devices-* tests
	work.
	* gcc.target/msp430/devices/bad-devices-1.c: New test.
	* gcc.target/msp430/devices/bad-devices-2.c: Likewise.
	* gcc.target/msp430/devices/bad-devices-3.c: Likewise.
	* gcc.target/msp430/devices/bad-devices-4.c: Likewise.
	* gcc.target/msp430/devices/bad-devices-5.c: Likewise.
	* gcc.target/msp430/devices/bad-devices-6.c: Likewise.
	* gcc.target/msp430/devices/csv-device-order.c: Likewise.
	* gcc.target/msp430/devices/csv-msp430_00.c: Likewise.
	* gcc.target/msp430/devices/csv-msp430_01.c: Likewise.
	* gcc.target/msp430/devices/csv-msp430_02.c: Likewise.
	* gcc.target/msp430/devices/csv-msp430_04.c: Likewise.
	* gcc.target/msp430/devices/csv-msp430_08.c: Likewise.
	* gcc.target/msp430/devices/csv-msp430_10.c: Likewise.
	* gcc.target/msp430/devices/csv-msp430_11.c: Likewise.
	* gcc.target/msp430/devices/csv-msp430_12.c: Likewise.
	* gcc.target/msp430/devices/csv-msp430_14.c: Likewise.
	* gcc.target/msp430/devices/csv-msp430_18.c: Likewise.
	* gcc.target/msp430/devices/csv-msp430_20.c: Likewise.
	* gcc.target/msp430/devices/csv-msp430_21.c: Likewise.
	* gcc.target/msp430/devices/csv-msp430_22.c: Likewise.
	* gcc.target/msp430/devices/csv-msp430_24.c: Likewise.
	* gcc.target/msp430/devices/csv-msp430_28.c: Likewise.
	* gcc.target/msp430/devices/csv-msp430fr5969.c: Likewise.
	* gcc.target/msp430/devices/hard-foo.c: Likewise.
	* gcc.target/msp430/devices/bad-devices-1.csv: New test support file.
	* gcc.target/msp430/devices/bad-devices-2.csv: Likewise.
	* gcc.target/msp430/devices/bad-devices-3.csv: Likewise.
	* gcc.target/msp430/devices/bad-devices-4.csv: Likewise.
	* gcc.target/msp430/devices/bad-devices-5.csv: Likewise.
	* gcc.target/msp430/devices/bad-devices-6.csv: Likewise.
	* gcc.target/msp430/devices/devices.csv: Likewise.

From-SVN: r274373

This patch makes predicate constants use the normal simd_immediate_info
machinery, rather than treating PFALSE and PTRUE as special cases.
This makes it easier to add other types of predicate constant later.

2019-08-13  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64-protos.h (aarch64_output_ptrue): Delete.
	* config/aarch64/aarch64-sve.md (*aarch64_sve_mov<PRED_ALL:mode>):
	Use a single Dn alternative instead of separate Dz and Dm
	alternatives.  Use aarch64_output_sve_move_immediate.
	* config/aarch64/aarch64.c (aarch64_sve_element_int_mode): New
	function.
	(aarch64_simd_valid_immediate): Fill in the simd_immediate_info
	for predicates too.
	(aarch64_output_sve_mov_immediate): Handle predicate modes.
	(aarch64_output_ptrue): Delete.

From-SVN: r274372

This patch tweaks the representation of SVE INDEX instructions in
simd_immediate_info so that it's easier to add new types of
constant on top.

2019-08-13  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64.c (simd_immediate_info::insn_type): Add
	INDEX.
	(simd_immediate_info::value, simd_immediate_info::step)
	(simd_immediate_info::modifier, simd_immediate_info::shift): Replace
	with...
	(simd_immediate_info::u): ...this new union.
	(simd_immediate_info::simd_immediate_info): Update accordingly.
	(aarch64_output_simd_mov_immediate): Likewise.
	(aarch64_output_sve_mov_immediate): Likewise.

From-SVN: r274371

gcc/ChangeLog:

2019-08-13  Jozef Lawrynowicz  <jozef.l@mittosystems.com>

	* gcc/config.gcc (msp430*-*-*): Add msp430-devices.o to extra_objs and
	extra_gcc_objs.
	* gcc/config/msp430/driver-msp430.c: Remove msp430_mcu_data.
	(msp430_select_cpu): New spec function.
	(msp430_select_hwmult_lib): Use msp430_extract_mcu_data to extract
	MCU data.
	* gcc/config/msp430/msp430-devices.c: New file.
	* gcc/config/msp430/msp430-devices.h: New file.
	* gcc/config/msp430/msp430.c: Remove msp430_mcu_data.
	(msp430_option_override): Use msp430_extract_mcu_data to extract
	MCU data.
	(msp430_use_f5_series_hwmult): Likewise.
	(use_32bit_hwmult): Likewise.
	(msp430_no_hwmult): Likewise.
	* gcc/config/msp430/msp430.h (ASM_SPEC): Don't pass -mmcu to the
	assembler.
	(DRIVER_SELF_SPECS): Call msp430_select_cpu if -mmcu is used without
	and -mcpu option.
	(EXTRA_SPEC_FUNCTIONS): Add msp430_select_cpu.
	* gcc/config/msp430/t-msp430: Add rule to build msp430-devices.o.
	Remove hard-coded MCU multilib data.

gcc/testsuite/ChangeLog:

2019-08-13  Jozef Lawrynowicz  <jozef.l@mittosystems.com>

	* gcc.target/msp430/msp430.exp
	(check_effective_target_msp430_430_selected): New.
	(check_effective_target_msp430_430x_selected): New.
	(check_effective_target_msp430_mlarge_selected): New.
	(check_effective_target_msp430_hwmul_not_none): New.
	(check_effective_target_msp430_hwmul_not_16bit): New.
	(check_effective_target_msp430_hwmul_not_32bit): New.
	(check_effective_target_msp430_hwmul_not_f5): New.
	(msp430_get_opts): New.
	(msp430_device_permutations_runtest): New.
	* gcc.target/msp430/devices/README: New file.
	* gcc.target/msp430/devices-main.c: New test.
	* gcc.target/msp430/devices/hard-cc430f5123.c: Likewise.
	* gcc.target/msp430/devices/hard-foo.c: Likewise.
	* gcc.target/msp430/devices/hard-msp430afe253.c: Likewise.
	* gcc.target/msp430/devices/hard-msp430cg4616.c: Likewise.
	* gcc.target/msp430/devices/hard-msp430f4783.c: Likewise.
	* gcc.target/msp430/devices/hard-rf430frl154h_rom.c: Likewise.

From-SVN: r274370

aarch64_classify_vector_mode used properties of a mode to test whether
the mode was a single Advanced SIMD vector, a single SVE vector, or a
tuple of SVE vectors.  That works well for current trunk and is simpler
than checking for modes by name.

However, for the ACLE and for planned autovec improvements, we also
need partial SVE vector modes that hold:

- half of the available 32-bit elements
- a half or quarter of the available 16-bit elements
- a half, quarter, or eighth of the available 8-bit elements

These should be packed in memory and unpacked in registers.  E.g.
VNx2SI has half the number of elements of VNx4SI, and so is half the
size in memory.  When stored in registers, each VNx2SI element occupies
the low 32 bits of a VNx2DI element, with the upper bits being undefined.

The upshot is that:

  GET_MODE_SIZE (VNx4SImode) == 2 * GET_MODE_SIZE (VNx2SImode)

since GET_MODE_SIZE must always be the memory size.  This in turn means
that for fixed-length SVE, some partial modes can have the same size as
Advanced SIMD modes.  We then need to be specific about which mode we're
dealing with.

This patch prepares for that by switching based on the mode instead
of querying properties.

A later patch makes sure that Advanced SIMD modes always win over
partial SVE vector modes in normal queries.

2019-08-13  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64.c (aarch64_classify_vector_mode): Switch
	based on the mode instead of testing properties of it.

From-SVN: r274368

Some indexed SVE FCMLA operations have a 3-bit register field that
requires one of Z0-Z7.  This patch adds a public "y" constraint for that.

The patch also documents "x", which is again intended to be a public
constraint.

2019-08-13  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* doc/md.texi: Document the x and y constraints for AArch64.
	* config/aarch64/aarch64.h (FP_LO8_REGNUM_P): New macro.
	(FP_LO8_REGS): New reg_class.
	(REG_CLASS_NAMES, REG_CLASS_CONTENTS): Add an entry for FP_LO8_REGS.
	* config/aarch64/aarch64.c (aarch64_hard_regno_nregs)
	(aarch64_regno_regclass, aarch64_class_max_nregs): Handle FP_LO8_REGS.
	* config/aarch64/predicates.md (aarch64_simd_register): Use
	FP_REGNUM_P instead of checking the classes manually.
	* config/aarch64/constraints.md (y): New constraint.

gcc/testsuite/
	* gcc.target/aarch64/asm-x-constraint-1.c: New test.
	* gcc.target/aarch64/asm-y-constraint-1.c: Likewise.

From-SVN: r274367

The Advanced SIMD and SVE permute patterns both split the permute
operation into a base name and a hilo suffix.  That works well, but it
means that for "@" patterns, we need to pass the permute code twice,
once for the base name and once for the suffix.

Having a unified name avoids that and also makes the definitions
slightly simpler.

2019-08-13  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/iterators.md (perm_insn): Include the "1"/"2" suffix.
	(perm_hilo): Remove UNSPEC_ZIP*, UNSEPC_TRN* and UNSPEC_UZP*.
	* config/aarch64/aarch64-simd.md
	(aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>): Rename to..
	(aarch64_<PERMUTE:perm_insn><mode>): ...this and remove perm_hilo
	from the asm template.
	* config/aarch64/aarch64-sve.md
	(aarch64_<perm_insn><perm_hilo><PRED_ALL:mode>): Rename to..
	(aarch64_<perm_insn><PRED_ALL:mode>): ...this and remove perm_hilo
	from the asm template.
	(aarch64_<perm_insn><perm_hilo><SVE_ALL:mode>): Rename to..
	(aarch64_<perm_insn><SVE_ALL:mode>): ...this and remove perm_hilo
	from the asm template.
	* config/aarch64/aarch64-simd-builtins.def: Update comment.

From-SVN: r274366

Correctly fill master_seed from os_seed.

From-SVN: r274365