* config/aarch64/aarch64-arches.def: Add "armv8.2-a".
	* config/aarch64/aarch64.h (AARCH64_FL_V8_2): New.
	(AARCH64_FL_F16): New.
	(AARCH64_FL_FOR_ARCH8_2): New.
	(AARCH64_ISA_8_2): New.
	(AARCH64_ISA_F16): New.
	(TARGET_FP_F16INST): New.
	(TARGET_SIMD_F16INST): New.
	* config/aarch64/aarch64-option-extensions.def ("fp16"): New entry.
	("fp"): Disabling "fp" also disables "fp16".
	* config/aarch64/aarch64-c.c (arch64_update_cpp_builtins): Conditionally define
	__ARM_FEATURE_FP16_SCALAR_ARITHMETIC and __ARM_FEATURE_FP16_VECTOR_ARITHMETIC.
	* doc/invoke.texi (AArch64 Options): Document "armv8.2-a" and "fp16".


Co-Authored-By: Jiong Wang <jiong.wang@arm.com>

From-SVN: r237956

Irrespective of the use of -o this so far resulted in "error: output
filename specified twice", since cc1_options already produces a -o
option when -S was specified.

gcc/
2016-07-04  Jan Beulich  <jbeulich@suse.com>

	* gcc.c (default_compilers["@c-header"]): Conditionalize "-o".

gcc/cp/
2016-07-04  Jan Beulich  <jbeulich@suse.com>

	* lang-specs.h ("@c++-header"): Conditionalize "-o".

gcc/testsuite/
2016-07-04  Jan Beulich  <jbeulich@suse.com>

	* g++.dg/header.c: New.
	* gcc.dg/header.c: New.

From-SVN: r237955

From-SVN: r237954

simd3.f90 and simd4.f90 fail only with -msse2.  But they are compiled
with -mavx on AVX machines.  Add 2 tests to compile simd3.f90 and
simd4.f90 with -msse2 on AVX machines.

	PR middle-end/71734
	* testsuite/libgomp.fortran/pr71734-1.f90: New test.
	* testsuite/libgomp.fortran/pr71734-2.f90: Likewise.

From-SVN: r237950

From-SVN: r237949

2016-07-02  François Dumont  <fdumont@gcc.gnu.org>

	* testsuite/23_containers/array/tuple_interface/get_debug_neg.cc: Adjust
	dg-error line numbers.
	* testsuite/23_containers/array/tuple_interface/
	tuple_element_debug_neg.cc: Likewise.
	* testsuite/25_algorithms/lexicographical_compare/debug/
	irreflexive_neg.cc: Remove.

From-SVN: r237945

	PR c/71719
	* c-typeck.c (mark_exp_read): Handle VIEW_CONVERT_EXPR.

	* c-c++-common/Wunused-var-15.c: New test.

From-SVN: r237937

From-SVN: r237936

	PR fortran/71687
	* f95-lang.c (struct binding_level): Add reversed field.
	(clear_binding_level): Adjust initializer.
	(getdecls): If reversed is clear, set it and nreverse the names
	chain before returning it.
	(poplevel): Use getdecls.
	* trans-decl.c (gfc_generate_function_code, gfc_process_block_locals):
	Use nreverse to pushdecl decls in the declaration order.

	* gfortran.dg/gomp/pr71687.f90: New test.

From-SVN: r237926

2016-07-01  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* gcc.dg/const-float128-ped.c: Require __float128 effective
	target and options.
	* gcc.dg/const-float128.c: Likewise.
	* gcc.dg/torture/float128-cmp-invalid.c: Require
	__float128 and base_quadfloat_support effective targets, and
	__float128 options.
	* gcc.dg/torture/float128-div-underflow.c: Likewise.
	* gcc.dg/torture/float128-extend-nan.c: Likewise.
	* gcc.dg/torture/float128-nan.c: Likewise.
	* gcc.dg/torture/fp-int-convert-float128-timode-2.c: Likewise.
	* gcc.dg/torture/fp-int-convert-float128-timode-3.c: Likewise.
	* gcc.dg/torture/fp-int-convert-float128-timode.c: Likewise.
	* lib/target-supports.exp (check_effective_target___float128):
	New.
	(add_options_for___float128): New.
	(check_effective_target_base_quadword_support): New.

From-SVN: r237924

From-SVN: r237921

[gcc]
2016-07-01  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/71720
	* config/rs6000/vsx.md (vsx_splat_v4sf_internal): When splitting
	the insns, use vsx_xxspltw_v4sf_direct which does not check for
	little endian.

[gcc/testsuite]
2016-07-01  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/71720
	* gcc.target/powerpc/pr71720.c: New test.

From-SVN: r237920

re PR fortran/71717 (A gfortran silent "wrong code" bug in the transition from 4.9.0 -> 4.9.1, using OpenMP.)

	PR fortran/71717
	* trans-openmp.c (gfc_omp_privatize_by_reference): Return false
	for GFC_DECL_ASSOCIATE_VAR_P with POINTER_TYPE.

	* testsuite/libgomp.fortran/associate3.f90: New test.

From-SVN: r237916

Just like gas, which has recently learned to reject such initializers,
gcc shouldn't accept such either.

gcc/
2016-07-01  Jan Beulich  <jbeulich@suse.com>

	* varasm.c (get_variable_section): Validate initializer in
	named .bss-like sections.

gcc/testsuite/
2016-07-01  Jan Beulich  <jbeulich@suse.com>

	* gcc.dg/bss.c: New.

From-SVN: r237913

altivec.md (*altivec_vpermr_<mode>_internal): Exchange the order of the second and third operands in the vpermr instruction...

gcc/ChangeLog:

2016-07-01  Kelvin Nilsen  <kelvin@gcc.gnu.org>

	* config/rs6000/altivec.md (*altivec_vpermr_<mode>_internal):
	Exchange the order of the second and third operands in the vpermr
	instruction tmeplate.

From-SVN: r237912

gcc/
	PR target/71698
	* config/rs6000/rs6000.c (rs6000_secondary_reload_simple_move): Disallow
	TDmode values.

gcc/testsuite/
	PR target/71698
	* gcc.target/powerpc/pr71698.c: New test.

From-SVN: r237911

re PR target/71151 ([avr] -fmerge-constants and -fdata-sections/-ffunction-sections results in string constants in .progmem.gcc_sw section)

gcc/testsuite/
	PR target/71151
	* gcc.target/avr/pr71151-common.h (foo): Use macro SECTION_NAME
	instead of ".foo" for its section name.
	* gcc.target/avr/pr71151-2.c (SECTION_NAME): Define appropriately
	depending on MCU's flash size.
	* gcc.target/avr/pr71151-3.c (SECTION_NAME): Dito.
	* gcc.target/avr/pr71151-4.c (SECTION_NAME): Dito.
	* gcc.target/avr/pr71151-5.c (SECTION_NAME): Dito.
	* gcc.target/avr/pr71151-6.c (SECTION_NAME): Dito.
	* gcc.target/avr/pr71151-7.c (SECTION_NAME): Dito.
	* gcc.target/avr/pr71151-8.c (SECTION_NAME): Dito.

From-SVN: r237910

For functions that return an argument unchanged, like strcat,
find_call_crossed_cheap_reg attempts to find an assignment between
a pseudo reg and the arg reg before the call, so that uses of the
pseudo after the call can instead use the return value.  The exit
condition on the loop looking at previous insns was wrong.  Uses of
the arg reg don't matter.  What matters is the insn setting the arg
reg as any assignment involving the arg reg prior to that insn is
likely a completely unrelated use of the hard reg.

	PR rtl-optimization/71709
	* ira-lives.c (find_call_crossed_cheap_reg): Exit loop on arg reg
	being set, not referenced.

From-SVN: r237909

I cannot see how without allowing the compiler to use SSE2 instructions
(as is done by all other tests for this PR scanning for particular
instructions) this test could ever have succeeded anywhere.

gcc/testsuite/
2016-07-01  Jan Beulich  <jbeulich@suse.com>

	* gcc.target/i386/pr65105-2.c: Add -msse2.

From-SVN: r237908

PR tree-optimization/70729

gcc/
	* tree-vectorizer.c (adjust_simduid_builtins): Nullify safelen field
	of loop since it can be not valid after transformation.

From-SVN: r237907

	* config/arm/arm.c (thumb_reload_in_hi): Delete.
	* config/arm/arm-protos.h (thumb_reload_in_hi): Delete prototype.

From-SVN: r237906

	* config/arm/arm.c (arm_function_ok_for_sibcall): Add another check
	for NULL decl.

From-SVN: r237903

From-SVN: r237902

2016-06-30  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/71677
	* config/rs6000/constraints.md (wY constraint): New constraint to
	match the requirements for the LXSD and STXSD instructions.
	* config/rs6000/predicates.md (offsettable_mem_14bit_operand): New
	predicate to match the requirements for the LXSD and STXSD
	instructions.
	* config/rs6000/rs6000.md (mov<mode>_hardfloat32, FMOVE64 case):
	Use constaint wY for LXSD/STXSD instructions instead of 'o' or 'Y'
	to make sure that the bottom 2 bits of offset are 0, the address
	form is offsettable, and no updating is done in the address mode.
	(mov<mode>_hardfloat64, FMOVE64 case): Likewise.
	(movdi_internal32): Likewise
	(movdi_internal64): Likewise.

From-SVN: r237898

	PR tree-optimization/71707
	* tree-ssa-strlen.c (get_stridx_plus_constant): Handle already present
	strinfo even for ADDR_EXPR ptr.

	* gcc.dg/strlenopt-29.c: New test.

From-SVN: r237889

	PR fortran/71704
	* parse.c (matchs, matcho): Move right before decode_omp_directive.
	If spec_only, only gfc_match the keyword and if successful, goto
	do_spec_only.
	(matchds, matchdo): Define.
	(decode_omp_directive): Add spec_only local var and set it.
	Use matchds or matchdo macros instead of matchs or matcho
	for declare target, declare simd, declare reduction and threadprivate
	directives.  Return ST_GET_FCN_CHARACTERISTICS if a non-declarative
	directive could be matched.
	(next_statement): For ST_GET_FCN_CHARACTERISTICS restore
	gfc_current_locus from old_locus even if there is no label.

	* gfortran.dg/gomp/pr71704.f90: New test.

From-SVN: r237888

	PR fortran/71705
	* trans-openmp.c (gfc_trans_omp_clauses): Set TREE_ADDRESSABLE on
	decls in to/from clauses.

	* gfortran.dg/gomp/pr71705.f90: New test.

From-SVN: r237887

gcc/ChangeLog:

2016-06-30  Kelvin Nilsen  <kelvin@gcc.gnu.org>

	* config/rs6000/altivec.md (darn_32): Change the condition to
	TARGET_P9_MISC instead of TARGET_MODULO.
	(darn_raw): Replace TARGET_MODULO with TARGET_P9_MISC in the
	condition expression.
	(darn): Replace TARGET_MODULO with TARGET_P9_MISC in the
	condition expression.
	* config/rs6000/dfp.md (UNSPEC_DTSTSFI): New unspec constant.
	(DFP_TEST): New code iterator.
	(dfptstsfi_<code>_mode>): New define_expand.
	(*dfp_sgnfcnc_<mode>): New define_insn.
	* config/rs6000/rs6000-builtin.def (BU_P9_MISC_0): Move this macro
	definition next to BU_P9_MISC_1 definition and change the MASK
	value to RS6000_BTM_P9_MISC.
	(BU_P9_MISC_1): Change the MASK value to RS6000_BTM_P9_MISC.
	(BU_P9_64BIT_MISC_0): Likewise.
	(BU_P9_DFP_MISC_0): New macro definition.
	(BU_P9_DFP_MISC_1): New macro definition.
	(BU_P9_DFP_MISC_2): New macro definition.
	(BU_P9_DFP_OVERLOAD_1): New macro definition.
	(BU_P9_DFP_OVERLOAD_2): New macro definition.
	(BU_P9_DFP_OVERLOAD_3): New macro definition.
	(TSTSFI_LT_DD): New BU_P9_DFP_MISC_2.
	(TSTSFI_LT_TD): Likewise.
	(TSTSFI_EQ_DD): Likewise.
	(TSTSFI_EQ_TD): Likewise.
	(TSTSFI_GT_DD): Likewise.
	(TSTSFI_GT_TD): Likewise.
	(TSTSFI_OV_DD): Likewise.
	(TSTSFI_OV_TD): Likewise.
	(TSTSFI_LT): New BU_P9_DFP_OVERLOAD_2.
	(TSTSFI_LT_DD): Likewise.
	(TSTSFI_LT_TD): Likewise.
	(TSTSFI_EQ): Likewise.
	(TSTSFI_EQ_DD): Likewise.
	(TSTSFI_EQ_TD): Likewise.
	(TSTSFI_GT): Likewise.
	(TSTSFI_GT_DD): Likewise.
	(TSTSFI_GT_TD): Likewise.
	(TSTSFI_OV): Likewise.
	(TSTSFI_OV_DD): Likewise.
	(TSTSFI_OV_TD): Likewise.
	* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
	overloaded test significance functions.
	* config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Add
	OPTION_MASK_P9_MISC into the representation of this mask.
	(POWERPC_MASKS): Add OPTION_MASK_P9_MISC into the representation
	of this mask.
	* config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Set the
	RS6000_BTM_P9_MISC flag in the return value if TARGET_P9_MISC is
	non-zero.
	(rs6000_expand_binop_builtin): Enforce that argument 0 of the exp
	argument is a 6-bit unsigned literal value if the icode argument
	represents a DFP test significance built-in call.
	(rs6000_invalid_builtin): Add support for the RS6000_BTM_P9_MISC
	flag used independently and in combination with the
	RS6000_BTM_64BIT flag.
	(rs6000_opt_masks): Add entry for power9-misc command-line option.
	(rs6000_builtin_mask_names): Add entry for power9-misc
	command-line option.
	* config/rs6000/rs6000.h: Redefine TARGET_P9_MISC as 0 if
	HAVE_AS_POWER9 is not a defined macro.  Define MASK_P9_MISC and
	RS6000_BTM_P9_MISC macros.
	* config/rs6000/rs6000.opt: Add support for the -mpower9-misc
	option and change the description of the -mpower9-vector option to
	enable only vector instructions, removing its erroneously claimed
	support for scalar instructions.
	* doc/extend.texi (PowerPC AltiVec Built-in Functions): Document
	the ISA 3.0 digital floating point test significance built-in
	functions.

gcc/testsuite/ChangeLog:

2016-06-30  Kelvin Nilsen  <kelvin@gcc.gnu.org>

	* gcc.target/powerpc/dfp/dfp.exp: New dejagnu test script.
	* gcc.target/powerpc/dfp/dtstsfi-0.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-1.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-10.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-11.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-12.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-13.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-14.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-15.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-16.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-17.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-18.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-19.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-2.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-20.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-21.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-22.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-23.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-24.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-25.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-26.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-27.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-28.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-29.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-3.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-30.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-31.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-32.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-33.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-34.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-35.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-36.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-37.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-38.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-39.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-4.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-40.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-41.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-42.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-43.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-44.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-45.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-46.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-47.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-48.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-49.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-5.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-50.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-51.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-52.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-53.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-54.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-55.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-56.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-57.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-58.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-59.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-6.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-60.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-61.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-62.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-63.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-64.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-65.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-66.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-67.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-68.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-69.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-7.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-70.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-71.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-72.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-73.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-74.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-75.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-76.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-77.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-78.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-79.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-8.c: New test.
	* gcc.target/powerpc/dfp/dtstsfi-9.c: New test.

From-SVN: r237885

This patch sets the branch cost to the same most optimal setting for all Cortex
cores, reducing codesize and improving performance due to using more CSEL
instructions.  Set the autoprefetcher model in Cortex-A72 to weak like the
others.  Enable AES fusion in Cortex-A35.  As a result generated code is now
more similar as well as more optimal across Cortex cores.

    gcc/
	* config/aarch64/aarch64.c (cortexa35_tunings):
	Enable AES fusion.  Use cortexa57_branch_cost.
	(cortexa53_tunings): Use cortexa57_branch_cost.
	(cortexa72_tunings): Use cortexa57_branch_cost.
	Use AUTOPREFETCHER_WEAK.
	(cortexa73_tunings): Use cortexa57_branch_cost.

From-SVN: r237884

2016-06-30  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
            James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/arm_neon.h (vcopyq_lane_f32, vcopyq_lane_f64,
	vcopyq_lane_p8, vcopyq_lane_p16, vcopyq_lane_s8, vcopyq_lane_s16,
	vcopyq_lane_s32, vcopyq_lane_s64, vcopyq_lane_u8, vcopyq_lane_u16,
	vcopyq_lane_u32, vcopyq_lane_u64): Reimplement in C.
	(vcopy_lane_f32, vcopy_lane_f64, vcopy_lane_p8, vcopy_lane_p16,
	vcopy_lane_s8, vcopy_lane_s16, vcopy_lane_s32, vcopy_lane_s64,
	vcopy_lane_u8, vcopy_lane_u16, vcopy_lane_u32, vcopy_lane_u64,
	vcopy_laneq_f32, vcopy_laneq_f64, vcopy_laneq_p8, vcopy_laneq_p16,
	vcopy_laneq_s8, vcopy_laneq_s16, vcopy_laneq_s32, vcopy_laneq_s64,
	vcopy_laneq_u8, vcopy_laneq_u16, vcopy_laneq_u32, vcopy_laneq_u64,
	vcopyq_laneq_f32, vcopyq_laneq_f64, vcopyq_laneq_p8, vcopyq_laneq_p16,
	vcopyq_laneq_s8, vcopyq_laneq_s16, vcopyq_laneq_s32, vcopyq_laneq_s64,
	vcopyq_laneq_u8, vcopyq_laneq_u16, vcopyq_laneq_u32, vcopyq_laneq_u64):
	New intrinsics.

	* gcc.target/aarch64/vect_copy_lane_1.c: New test.


Co-Authored-By: James Greenhalgh <james.greenhalgh@arm.com>

From-SVN: r237883

2016-06-30  James Greenhalgh  <james.greenhalgh@arm.com>
            Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/aarch64/aarch64-simd.md (*aarch64_simd_vec_copy_lane<mode>):
	New define_insn.
	(*aarch64_simd_vec_copy_lane_<vswap_width_name><mode>): Likewise.

	* gcc.target/aarch64/vget_set_lane_1.c: New test.


Co-Authored-By: Kyrylo Tkachov <kyrylo.tkachov@arm.com>

From-SVN: r237882

gcc/ChangeLog:
	PR driver/71651
	* gcc.c (driver::build_option_suggestions): Pass "option" to
	add_misspelling_candidates.
	* opts-common.c (add_misspelling_candidates): Add "option" param;
	use it to avoid adding negated forms for options marked with
	RejectNegative.
	* opts.h (add_misspelling_candidates): Add "option" param.

gcc/testsuite/ChangeLog:
	PR driver/71651
	* gcc.dg/spellcheck-options-12.c: New test case.

From-SVN: r237880

2016-06-30  Thomas Preud'homme  <thomas.preudhomme@arm.com>

libstdc++-v3/
    * testsuite/29_atomics/atomic/65913.cc: Require atomic-builtins rather
    than specific target.

From-SVN: r237879

re PR middle-end/71693 (ICE: verify_gimple failed (type mismatch in shift expression, -O0, -O1, -O2, -O3))

	PR middle-end/71693
	* fold-const.c (fold_binary_loc) <case RROTATE_EXPR>: Cast
	TREE_OPERAND (arg0, 0) and TREE_OPERAND (arg0, 1) to type
	first when permuting bitwise operation with rotate.  Cast
	TREE_OPERAND (arg0, 0) to type when cancelling two rotations.

	* gcc.c-torture/compile/pr71693.c: New test.

From-SVN: r237875

From-SVN: r237869

gcc/ChangeLog:
	* opts.c (handle_param): Use find_param_fuzzy to offer suggestions
	for misspelled param names.
	* params.c: Include spellcheck.h.
	(find_param_fuzzy): New function.
	* params.h (find_param_fuzzy): New prototype.
	* spellcheck.c (struct edit_distance_traits<const char *>): Move
	to...
	* spellcheck.h (struct edit_distance_traits<const char *>):
	...here.

gcc/testsuite/ChangeLog:
	* gcc.dg/spellcheck-params.c: New testcase.
	* gcc.dg/spellcheck-params-2.c: New testcase.

From-SVN: r237865

[gcc]
2016-06-29  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/predicates.md (const_0_to_7_operand): New
	predicate, recognize 0..7.
	* config/rs6000/rs6000.c (rs6000_expand_vector_extract): Add
	support for doing extracts from V16QImode, V8HImode, V4SImode
	under ISA 3.0.
	* config/rs6000/vsx.md (VSX_EXTRACT_I): Mode iterator for ISA 3.0
	vector extract support.
	(VSX_EXTRACT_PREDICATE): Mode attribute to validate element number
	for ISA 3.0 vector extract.
	(VSX_EX): Constraints to use for ISA 3.0 vector extract.
	(vsx_extract_<mode>, VSX_EXTRACT_I): Add support for doing
	extracts of a constant element number from small integer vectors
	on 64-bit ISA 3.0 systems.
	(vsx_extract_<mode>_di): Likewise.
	* config/rs6000/rs6000.h (TARGET_VEXTRACTUB): New target macro to
	say when we can do ISA 3.0 vector extracts.
	* config/rs6000/rs6000.md (stfiwx): Allow DImode in Altivec
	registers, using the stxsiwx instruction.

[gcc/testsuite]
2016-06-29  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/p9-extract-1.c: New file to test ISA 3.0
	vector extract instructions.
	* gcc.target/powerpc/p9-extract-2.c: Likewise.

From-SVN: r237864

2016-06-29  Jerry DeLisle  <jvdelisle@gcc.gnu.org>

	PR fortran/71686
	* gfortran.dg/unexpected_eof_2.f90: New test.
	* gfortran.dg/unexpected_eof_3.f90: New test.

From-SVN: r237861

2016-06-29  Jerry DeLisle  <jvdelisle@gcc.gnu.org>

	PR fortran/71686
	* scanner.c (gfc_next_char_literal): Only decrement nextc if it
	is not NULL.

From-SVN: r237860

	gcc/
	* config/aarch64/aarch64-cores.def (qdf24xx): Use qdf24xx tuning.
	* config/aarch64/aarch64.c (qdf24xx_addrcost_table,
	qdf24xx_regmove_cost, qdf24xx_tunings): New.
	* config/arm/aarch64-cost-tables.h (qdf24xx_extra_costs): New.
	* config/arm/arm-cores.def (qdf24xx): Use qdf24xx tuning.
	* config/arm/arm.c (arm_qdf24xx_tune): New.

	gcc/testsuite/
	* gcc.dg/asr_div1.c: Add aarch64 specific dg-options.

From-SVN: r237857