From-SVN: r279788

	* config/vxworks/_yvals.h: New file.
	* config/vxworks/_yvals-wrapper.h: New file.
	* config/vxworks/math.h: Use it to wrap the VxWorks
	math.h header.
	* config/vxworks/complex.h: Likewise.
	* config/vxworks/setjmp.h: Likewise.
	* config/vxworks/inttypes.h: Likewise.

From-SVN: r279787

	* config/vxworks/_vxworks-versions.h: New File.

From-SVN: r279786

From-SVN: r279785

Starting from VxWorks 7, the system comes with a Dinkumware
environment which requires the inclusion of "yvals.h" before other
system headers.  We provide wrapped versions of a few headers to
accommodate such constraints.

2019-12-30  Jerome Lambourg  <lambourg@adaccore.com>
            Olivier Hainque  <hainque@adacore.com>

	gcc/
	* config/vxworks/_yvals.h: New file.
	* config/vxworks/_yvals-wrapper.h: New file.
	* gcc/config/vxworks/math.h: Use it to wrap the VxWorks
	math.h header.
	* gcc/config/vxworks/complex.h: Likewise.
	* gcc/config/vxworks/setjmp.h: Likewise.
	* gcc/config/vxworks/inttypes.h: Likewise.
	* config.gcc (*-*-vxworks*): Add system header wrappers
	to extra_headers.
	(powerpc-*-vxworks*): Reuse the common extra_headers.

From-SVN: r279784

This changes introduces an internal API for VxWorks version checks
within runtime files, a prerequisite to a few fixes coming up for libstdc++
builds on more recent versions of the OS.

2019-12-30  Olivier Hainque  <hainque@adacore.com>

	gcc/
	* config/vxworks/_vxworks-versions.h: New file.
	* config.gcc (*-*-vxworks*): Add it to extra_headers.

	libgcc/
	* config/gthr-vxworks.h: Use _vxworks-versions.h.
	* config/gthr-vxworks-tls.c: Likewise.

From-SVN: r279783

2019-12-30  Olivier Hainque  <hainque@adacore.com>

	* config/t-vxworks: Rework the vxworks.o compilation
	rules to use $(COMPILE).

From-SVN: r279782

This patch modifies the C & C++ VxWorks compiler to predefine
the __STDC_ macros verified by gcc.dg/c99-predef-1.c in the testsuite.

2019-12-13  Joel Brobecker  <brobecker@adacore.com>

	* config.gcc <*-*-vxworks*>: Add vxworks-c.o to c_target_objs
	and cxx_target_objs. Set target_has_targetcm to "yes". Add
	vxworks-predef.h to extra_headers.
	* config/t-vxworks (vxworks-c.o): New target.
	* config/vxworks-c.c: New file.
	* config/vxworks/vxworks-predef.h: New file.

From-SVN: r279781

This change refines the VxWorks macro definitions configuring
wchar_t to accommodate the VxWorks7 environment, where wchar_t
is now typically a 32bit type.

We also ensure that the definitions for wint_t are always based
on those for wchar_t, so the two remain in sync in environments
where WCHAR_TYPE is redefined for a specific CPU architecture.

2019-12-30  Alexandre Oliva  <oliva@adacore.com>
           Olivier Hainque  <hainque@adacore.com>

	* config/vx-common.h (WCHAR_TYPE_SIZE): 32 on VxWorks 7.
	(WCHAR_TYPE): Pick accordingly.
	(WINT_TYPE_SIZE): Define in terms of WCHAR_TYPE_SIZE.
	(WINT_TYPE): Define in terms of WCHAR_TYPE.

Co-Authored-By: Olivier Hainque <hainque@adacore.com>

From-SVN: r279780

2019-12-30  Olivier Hainque  <hainque@adacore.com>

        * config/vx-common.h: Minor reorganization and add
        sectioning comments.

From-SVN: r279779

2019-12-30  Doug Rupp  <rupp@adacore.com>

	* config/rs6000/vxworks.h (STARTFILE_PREFIX_SPEC): Define.

From-SVN: r279778

2019-12-30  Olivier Hainque  <hainque@adacore.com>
            Jerome Lambourg  <labourg@adacore.com>

   	* config/t-vxworks: Arrange to alter/restore glimits.h
   	before/after stmp-int-hdrs, so it uses a different macro
   	name to protect itself against recursive inclusions.

Co-Authored-By: Jerome Lambourg <lambourg@adacore.com>

From-SVN: r279777

2019-12-30  Olivier Hainque  <hainque@adacore.com>

	* config/gthr-vxworks.h (GTHREAD_ONCE_INIT): Use
	standard zero-initializer syntax.

From-SVN: r279776

2019-12-30  Olivier Hainque  <hainque@adacore.com>

	libgcc/
	* config/gthr-vxworks-tls.c (__gthread_getspecific): Fix
	reference to the internal VX_GET_TLS_DATA interface.

From-SVN: r279775

2019-12-30  Olivier Hainque  <hainque@adacore.com>

	libgcc/
	* config/vxcrtstuff.c: Fix incorrect spelling of
	USE_INITFINI_ARRAY in guard.

From-SVN: r279774

	PR libgomp/93066
	* inclhack.def (hpux_c99_inttypes3): Fix defines for INTPTR_MAX
	and UINTPTR_MAX, and missing define for SIZE_MAX.
	* fixincl.x: Regenerate.
	* tests/base/inttypes.h: Update for above fix.

From-SVN: r279773

gcc/
	PR target/92923
	* config/rs6000/rs6000-builtin.def (VAND, VANDC, VNOR, VOR, VXOR):
	Delete.
	(EQV_V16QI_UNS, EQV_V8HI_UNS, EQV_V4SI_UNS, EQV_V2DI_UNS, EQV_V1TI_UNS,
	NAND_V16QI_UNS, NAND_V8HI_UNS, NAND_V4SI_UNS, NAND_V2DI_UNS,
	NAND_V1TI_UNS, ORC_V16QI_UNS, ORC_V8HI_UNS, ORC_V4SI_UNS, ORC_V2DI_UNS,
	ORC_V1TI_UNS, VAND_V16QI_UNS, VAND_V16QI, VAND_V8HI_UNS, VAND_V8HI,
	VAND_V4SI_UNS, VAND_V4SI, VAND_V2DI_UNS, VAND_V2DI, VAND_V4SF,
	VAND_V2DF, VANDC_V16QI_UNS, VANDC_V16QI, VANDC_V8HI_UNS, VANDC_V8HI,
	VANDC_V4SI_UNS, VANDC_V4SI, VANDC_V2DI_UNS, VANDC_V2DI, VANDC_V4SF,
	VANDC_V2DF, VNOR_V16QI_UNS, VNOR_V16QI, VNOR_V8HI_UNS, VNOR_V8HI,
	VNOR_V4SI_UNS, VNOR_V4SI, VNOR_V2DI_UNS, VNOR_V2DI, VNOR_V4SF,
	VNOR_V2DF, VOR_V16QI_UNS, VOR_V16QI, VOR_V8HI_UNS, VOR_V8HI,
	VOR_V4SI_UNS, VOR_V4SI, VOR_V2DI_UNS, VOR_V2DI, VOR_V4SF, VOR_V2DF,
	VXOR_V16QI_UNS, VXOR_V16QI, VXOR_V8HI_UNS, VXOR_V8HI,
	VXOR_V4SI_UNS, VXOR_V4SI, VXOR_V2DI_UNS, VXOR_V2DI, VXOR_V4SF,
	VXOR_V2DF): Add definitions.
	* config/rs6000/rs6000-call.c (altivec_overloaded_builtins)
	<ALTIVEC_BUILTIN_VAND, ALTIVEC_BUILTIN_VANDC, ALTIVEC_BUILTIN_VNOR,
	ALTIVEC_BUILTIN_VOR, ALTIVEC_BUILTIN_VXOR>: Remove.
	<ALTIVEC_BUILTIN_VAND_V4SF, ALTIVEC_BUILTIN_VAND_V2DF,
	ALTIVEC_BUILTIN_VAND_V2DI, ALTIVEC_BUILTIN_VAND_V2DI_UNS,
	ALTIVEC_BUILTIN_VAND_V4SI_UNS, ALTIVEC_BUILTIN_VAND_V4SI,
	ALTIVEC_BUILTIN_VAND_V8HI_UNS, ALTIVEC_BUILTIN_VAND_V8HI,
	ALTIVEC_BUILTIN_VAND_V16QI, ALTIVEC_BUILTIN_VAND_V16QI_UNS,
	ALTIVEC_BUILTIN_VANDC_V4SF, ALTIVEC_BUILTIN_VANDC_V2DF,
	ALTIVEC_BUILTIN_VANDC_V2DI, ALTIVEC_BUILTIN_VANDC_V2DI_UNS,
	ALTIVEC_BUILTIN_VANDC_V4SI_UNS, ALTIVEC_BUILTIN_VANDC_V4SI,
	ALTIVEC_BUILTIN_VANDC_V8HI_UNS, ALTIVEC_BUILTIN_VANDC_V8HI,
	ALTIVEC_BUILTIN_VANDC_V16QI, ALTIVEC_BUILTIN_VANDC_V16QI_UNS,
	ALTIVEC_BUILTIN_VNOR_V4SF, ALTIVEC_BUILTIN_VNOR_V2DF,
	ALTIVEC_BUILTIN_VNOR_V2DI, ALTIVEC_BUILTIN_VNOR_V2DI_UNS,
	ALTIVEC_BUILTIN_VNOR_V4SI, ALTIVEC_BUILTIN_VNOR_V4SI_UNS,
	ALTIVEC_BUILTIN_VNOR_V8HI, ALTIVEC_BUILTIN_VNOR_V8HI_UNS,
	ALTIVEC_BUILTIN_VNOR_V16QI, ALTIVEC_BUILTIN_VNOR_V16QI_UNS,
	ALTIVEC_BUILTIN_VOR_V4SF, ALTIVEC_BUILTIN_VOR_V2DF,
	ALTIVEC_BUILTIN_VOR_V2DI, ALTIVEC_BUILTIN_VOR_V2DI_UNS,
	ALTIVEC_BUILTIN_VOR_V4SI_UNS, ALTIVEC_BUILTIN_VOR_V4SI,
	ALTIVEC_BUILTIN_VOR_V8HI_UNS, ALTIVEC_BUILTIN_VOR_V8HI,
	ALTIVEC_BUILTIN_VOR_V16QI, ALTIVEC_BUILTIN_VOR_V16QI_UNS,
	ALTIVEC_BUILTIN_VXOR_V4SF, ALTIVEC_BUILTIN_VXOR_V2DF,
	ALTIVEC_BUILTIN_VXOR_V2DI, ALTIVEC_BUILTIN_VXOR_V2DI_UNS,
	ALTIVEC_BUILTIN_VXOR_V4SI_UNS, ALTIVEC_BUILTIN_VXOR_V4SI,
	ALTIVEC_BUILTIN_VXOR_V8HI, ALTIVEC_BUILTIN_VXOR_V8HI_UNS,
	ALTIVEC_BUILTIN_VXOR_V16QI, ALTIVEC_BUILTIN_VXOR_V16QI_UNS>: Add
	definitions.
	<P8V_BUILTIN_EQV_V16QI, P8V_BUILTIN_EQV_V8HI, P8V_BUILTIN_EQV_V4SI,
	P8V_BUILTIN_EQV_V2DI, P8V_BUILTIN_NAND_V16QI, P8V_BUILTIN_NAND_V8HI,
	P8V_BUILTIN_NAND_V4SI, P8V_BUILTIN_NAND_V2DI, P8V_BUILTIN_ORC_V16QI,
	P8V_BUILTIN_ORC_V8HI, P8V_BUILTIN_ORC_V4SI,
	P8V_BUILTIN_ORC_V2DI>: Change unsigned usages to use the new *_UNS
	definition names.
	(rs6000_gimple_fold_builtin) <ALTIVEC_BUILTIN_VAND_V16QI_UNS,
	ALTIVEC_BUILTIN_VAND_V16QI, ALTIVEC_BUILTIN_VAND_V8HI_UNS,
	ALTIVEC_BUILTIN_VAND_V8HI, ALTIVEC_BUILTIN_VAND_V4SI_UNS,
	ALTIVEC_BUILTIN_VAND_V4SI, ALTIVEC_BUILTIN_VAND_V2DI_UNS,
	ALTIVEC_BUILTIN_VAND_V2DI, ALTIVEC_BUILTIN_VAND_V4SF,
	ALTIVEC_BUILTIN_VAND_V2DF, ALTIVEC_BUILTIN_VANDC_V16QI_UNS,
	ALTIVEC_BUILTIN_VANDC_V16QI, ALTIVEC_BUILTIN_VANDC_V8HI_UNS,
	ALTIVEC_BUILTIN_VANDC_V8HI, ALTIVEC_BUILTIN_VANDC_V4SI_UNS,
	ALTIVEC_BUILTIN_VANDC_V4SI, ALTIVEC_BUILTIN_VANDC_V2DI_UNS,
	ALTIVEC_BUILTIN_VANDC_V2DI, ALTIVEC_BUILTIN_VANDC_V4SF,
	ALTIVEC_BUILTIN_VANDC_V2DF, P8V_BUILTIN_NAND_V16QI_UNS,
	P8V_BUILTIN_NAND_V8HI_UNS, P8V_BUILTIN_NAND_V4SI_UNS,
	P8V_BUILTIN_NAND_V2DI_UNS, P8V_BUILTIN_NAND_V2DI,
	ALTIVEC_BUILTIN_VOR_V16QI_UNS, ALTIVEC_BUILTIN_VOR_V16QI,
	ALTIVEC_BUILTIN_VOR_V8HI_UNS, ALTIVEC_BUILTIN_VOR_V8HI,
	ALTIVEC_BUILTIN_VOR_V4SI_UNS, ALTIVEC_BUILTIN_VOR_V4SI,
	ALTIVEC_BUILTIN_VOR_V2DI_UNS, ALTIVEC_BUILTIN_VOR_V2DI,
	ALTIVEC_BUILTIN_VOR_V4SF, ALTIVEC_BUILTIN_VOR_V2DF,
	P8V_BUILTIN_ORC_V16QI_UNS, P8V_BUILTIN_ORC_V8HI_UNS,
	P8V_BUILTIN_ORC_V4SI_UNS, P8V_BUILTIN_ORC_V2DI_UNS,
	P8V_BUILTIN_ORC_V2DI, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
	ALTIVEC_BUILTIN_VXOR_V16QI, ALTIVEC_BUILTIN_VXOR_V8HI_UNS,
	ALTIVEC_BUILTIN_VXOR_V8HI, ALTIVEC_BUILTIN_VXOR_V4SI_UNS,
	ALTIVEC_BUILTIN_VXOR_V4SI, ALTIVEC_BUILTIN_VXOR_V2DI_UNS,
	ALTIVEC_BUILTIN_VXOR_V2DI, ALTIVEC_BUILTIN_VXOR_V4SF,
	ALTIVEC_BUILTIN_VXOR_V2DF, ALTIVEC_BUILTIN_VNOR_V16QI_UNS,
	ALTIVEC_BUILTIN_VNOR_V16QI, ALTIVEC_BUILTIN_VNOR_V8HI_UNS,
	ALTIVEC_BUILTIN_VNOR_V8HI, ALTIVEC_BUILTIN_VNOR_V4SI_UNS,
	ALTIVEC_BUILTIN_VNOR_V4SI, ALTIVEC_BUILTIN_VNOR_V2DI_UNS,
	ALTIVEC_BUILTIN_VNOR_V2DI, ALTIVEC_BUILTIN_VNOR_V4SF,
	ALTIVEC_BUILTIN_VNOR_V2DF>: Use new definition names.
	(builtin_function_type) <ALTIVEC_BUILTIN_VAND_V16QI_UNS,
	ALTIVEC_BUILTIN_VAND_V8HI_UNS, ALTIVEC_BUILTIN_VAND_V4SI_UNS,
	ALTIVEC_BUILTIN_VAND_V2DI_UNS, ALTIVEC_BUILTIN_VANDC_V16QI_UNS,
	ALTIVEC_BUILTIN_VANDC_V8HI_UNS, ALTIVEC_BUILTIN_VANDC_V4SI_UNS,
	ALTIVEC_BUILTIN_VANDC_V2DI_UNS, ALTIVEC_BUILTIN_VNOR_V16QI_UNS,
	ALTIVEC_BUILTIN_VNOR_V8HI_UNS, ALTIVEC_BUILTIN_VNOR_V4SI_UNS,
	ALTIVEC_BUILTIN_VNOR_V2DI_UNS, ALTIVEC_BUILTIN_VOR_V16QI_UNS,
	ALTIVEC_BUILTIN_VOR_V8HI_UNS, ALTIVEC_BUILTIN_VOR_V4SI_UNS,
	ALTIVEC_BUILTIN_VOR_V2DI_UNS, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
	ALTIVEC_BUILTIN_VXOR_V8HI_UNS, ALTIVEC_BUILTIN_VXOR_V4SI_UNS,
	ALTIVEC_BUILTIN_VXOR_V2DI_UNS, P8V_BUILTIN_EQV_V16QI_UNS,
	P8V_BUILTIN_EQV_V8HI_UNS, P8V_BUILTIN_EQV_V4SI_UNS,
	P8V_BUILTIN_EQV_V2DI_UNS, P8V_BUILTIN_EQV_V1TI_UNS,
	P8V_BUILTIN_NAND_V16QI_UNS, P8V_BUILTIN_NAND_V8HI_UNS,
	P8V_BUILTIN_NAND_V4SI_UNS, P8V_BUILTIN_NAND_V2DI_UNS,
	P8V_BUILTIN_NAND_V1TI_UNS, P8V_BUILTIN_ORC_V16QI_UNS,
	P8V_BUILTIN_ORC_V8HI_UNS, P8V_BUILTIN_ORC_V4SI_UNS,
	P8V_BUILTIN_ORC_V2DI_UNS, P8V_BUILTIN_ORC_V1TI_UNS>: Handle unsigned
	builtins.

gcc/testsuite/
       PR target/92923
       * gcc.target/powerpc/pr92923-1.c: New test.
       * gcc.target/powerpc/pr92923-2.c: Likewise.

From-SVN: r279772

Asserting !BRACE_ENCLOSED_INITIALIZER_P seems pretty pointless, since
that checks for init_list_type_node, and a compound literal won't have
that type, nor will we see that type if we just checked that it's
something else.

	* decl.c (reshape_init_r): Remove assert.

From-SVN: r279771

/gcc/cp
2019-12-30  Paolo Carlini  <paolo.carlini@oracle.com>

	* decl2.c (delete_sanity): Add location_t parameter and use
	it throughout.
	* init.c (build_vec_delete_1): Likewise.
	(build_delete): Likewise.
	(build_vec_delete): Likewise.
	(perform_target_ctor): Adjust call.
	(perform_member_init): Likewise.
	(build_vec_init): Likewise.
	* decl.c (cxx_maybe_build_cleanup): Likewise.
	* pt.c (tsubst_copy_and_build): Likewise.
	* parser.c (cp_parser_delete_expression): Likewise, pass the
	combined_loc.
	* cp-tree.h: Update declarations.

/libcc1
2019-12-30  Paolo Carlini  <paolo.carlini@oracle.com>

	* libcp1plugin.cc (plugin_build_unary_expr): Update delete_sanity
	call.

/gcc/testsuite
2019-12-30  Paolo Carlini  <paolo.carlini@oracle.com>

	* g++.dg/init/delete1.C: Check locations too.
	* g++.dg/ipa/pr85607.C: Likewise.
	* g++.dg/warn/Wdelete-incomplete-1.C: Likewise.
	* g++.dg/warn/delete-non-virtual-dtor.C: Likewise.
	* g++.dg/warn/incomplete1.C: Likewise.

From-SVN: r279768

2019-12-30  Thomas Koenig  <tkoenig@gcc.gnu.org>

	PR fortran/91651
	* gfortran.dg/index_3.f90: Fix PR number.

From-SVN: r279766

2019-12-30  Thomas Koenig  <tkoenig@gcc.gnu.org>

	PR fortran/91651
	Fix PR numbers in ChangeLog.

From-SVN: r279765

2019-12-30  Thomas Koenig  <tkoenig@gcc.gnu.org>

	PR fortran/91541
	* intrinsic.c (add_sym_4ind): New function.
	(add_functions): Use it for INDEX.
	(resolve_intrinsic): Also call f1m for INDEX.
	* intrinsic.h (gfc_resolve_index_func): Adjust prototype to
	take a gfc_arglist instead of individual arguments.
	* iresolve.c (gfc_resolve_index_func): Adjust arguments.
	Remove KIND argument if present, and make sure this is
	not done twice.
	* trans-decl.c: Include "intrinsic.h".
	(gfc_get_extern_function_decl): Special case for resolving INDEX.

2019-12-30  Thomas Koenig  <tkoenig@gcc.gnu.org>

	PR fortran/91541
	* gfortran.dg/index_3.f90: New test.

From-SVN: r279763

2019-12-30  Thomas Koenig  <tkoenig@gcc.gnu.org>

	PR fortran/92961
	* gfortran.h (gfc_seen_div0): Add declaration.
	* arith.h (gfc_seen_div0): Add definition.
	(eval_intrinsic): For integer division by zero, set gfc_seen_div0.
	* decl.c (variable_decl):  If resolution resp. simplification
	fails for array spec and a division of zero error has been
	seen, return MATCH_ERROR.

2019-12-30  Thomas Koenig  <tkoenig@gcc.gnu.org>

	PR fortran/92961
	* gfortran.dg/arith_divide_2.f90: New test.

From-SVN: r279762

From-SVN: r279761

	PR c++/92745
	* g++.dg/cpp0x/initlist118.C: Add -Wno-psabi -w to dg-options.

From-SVN: r279758

This patch implements
<http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2018/p1327r1.html>.

When build_dynamic_cast realizes that a dynamic_cast needs a run-time check, it
generates a call to __dynamic_cast -- see dyncast.cc in libsupc++ for its
definition.  The gist of my approach is to evaluate such a call at compile time.

	* constexpr.c (cxx_dynamic_cast_fn_p): New function.
	(extract_obj_from_addr_offset): New function.
	(get_component_with_type): New function.
	(cxx_eval_dynamic_cast_fn): New function.
	(cxx_eval_call_expression): Call cxx_eval_dynamic_cast_fn for a call
	to __dynamic_cast.
	(potential_constant_expression_1): Don't give up on
	cxx_dynamic_cast_fn_p.
	* rtti.c (build_dynamic_cast_1): When creating a call to
	__dynamic_cast, use the location of the original expression.

	* g++.dg/cpp2a/constexpr-dynamic1.C: New test.
	* g++.dg/cpp2a/constexpr-dynamic10.C: New test.
	* g++.dg/cpp2a/constexpr-dynamic11.C: New test.
	* g++.dg/cpp2a/constexpr-dynamic12.C: New test.
	* g++.dg/cpp2a/constexpr-dynamic13.C: New test.
	* g++.dg/cpp2a/constexpr-dynamic14.C: New test.
	* g++.dg/cpp2a/constexpr-dynamic15.C: New test.
	* g++.dg/cpp2a/constexpr-dynamic16.C: New test.
	* g++.dg/cpp2a/constexpr-dynamic17.C: New test.
	* g++.dg/cpp2a/constexpr-dynamic2.C: New test.
	* g++.dg/cpp2a/constexpr-dynamic3.C: New test.
	* g++.dg/cpp2a/constexpr-dynamic4.C: New test.
	* g++.dg/cpp2a/constexpr-dynamic5.C: New test.
	* g++.dg/cpp2a/constexpr-dynamic6.C: New test.
	* g++.dg/cpp2a/constexpr-dynamic7.C: New test.
	* g++.dg/cpp2a/constexpr-dynamic8.C: New test.
	* g++.dg/cpp2a/constexpr-dynamic9.C: New test.

From-SVN: r279755

	PR target/93078
	* config/i386/i386-builtins.c (ix86_builtin_vectorized_function):
	Remove CASE_CFN_RINT handling.
	* config/i386/i386-builtin.def (IX86_BUILTIN_RINTPD,
	IX86_BUILTIN_RINTPS, IX86_BUILTIN_RINTPD256, IX86_BUILTIN_RINTPS256):
	Remove.
	* config/i386/sse.md (nearbyint<mode>2, rint<mode>2): New expanders
	with VF iterator.

	* gcc.target/i386/sse4_1-pr93078.c: New test.
	* gcc.target/i386/avx-pr93078.c: New test.
	* gcc.target/i386/avx512f-pr93078.c: New test.

From-SVN: r279754

In this testcase we use an unmasked SVE loop with an Advanced SIMD
epilogue (because we don't yet support fully-masked downward loops).
The main loop uses a gather load for the strided access while the
epilogue loop builds the access from scalars instead.  In both cases
we gimplify expressions based on the DR_STEP and insert them in the
loop preheader.

The problem was that the gather load code didn't copy the DR_STEP before
gimplifying it, meaning that the epilogue loop tried to reuse a result
from the (non-dominating) main loop preheader.

It looks at first glance like there could be other instances of this too,
but this patch just deals with the gather/scatter case.

2019-12-29  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* tree-vect-stmts.c (vect_get_strided_load_store_ops): Copy
	DR_STEP before gimplifying it.

gcc/testsuite/
	* gcc.dg/vect/vect-strided-epilogue-1.c: New test.

From-SVN: r279753

The EXTRACT_LAST_REDUCTION handling needs to generate a separate
comparison instruction that feeds the vector mask argument of the
IFN_EXTRACT_LAST call.  We weren't checking whether that comparison
was supported, leading to an ICE on the testcase.

2019-12-29  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* tree-vect-stmts.c (vectorizable_condition): For extract-last
	reductions, check that the target supports the required comparison
	operation.

gcc/testsuite/
	* gcc.dg/vect/vect-cond-12.c: New test.

From-SVN: r279752

From-SVN: r279751

	PR bootstrap/93074
	* plugin/cuda/cuda.h (cuDeviceGetName, cuDriverGetVersion): Declare.
	(cuDeviceTotalMem, cuMemGetInfo): Likewise.  Define to *_v2.

From-SVN: r279747

From-SVN: r279746

All VNx2 V_INT_CONTAINER entries should map to VNx2DI.  The lower-case
version was already correct.

2019-12-27  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/iterators.md (V_INT_CONTAINER): Fix VNx2SF entry.

gcc/testsuite/
	* gcc.target/aarch64/sve/mixed_size_11.c: New test.

From-SVN: r279743

The fold-left reduction code has a (rarely-used) fallback that handles
cases in which the loop is fully-masked and the target has no native
support for the reduction.  The fallback includea a VEC_COND_EXPR
between the reduction vector and a safe value, so we should check
whether that VEC_COND_EXPR is supported.

2019-12-27  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* tree-vect-loop.c (vectorizable_reduction): Check whether the
	target supports the required VEC_COND_EXPR operation before
	allowing the fallback handling of masked fold-left reductions.

gcc/testsuite/
	* gcc.target/aarch64/sve/mixed_size_10.c: New test.

From-SVN: r279742

From-SVN: r279739

	PR c++/92438
	* parser.c (cp_parser_constructor_declarator_p): If open paren
	is followed by RID_ATTRIBUTE, skip over the attribute tokens and
	try to parse type specifier.

	* g++.dg/ext/attrib61.C: New test.

From-SVN: r279736

From-SVN: r279735

When cross-building for vxworks, test for declarations of long double
functions in math.h.  We don't normally test for these functions when
cross compiling, because link tests don't work, or ever really, but
not defining them as available causes replacements to be defined in
ways that may cause duplicate definition linker errors if the units
defining both the replacement and the actual implementation are
brought in because of other symbols.


for libstdc++-v3/ChangeLog

	* crossconfig.m4 (GLIBCXX_CROSSCONFIG) [*-vxworks*]: Define
	long double functions as available if declared by math.h.
	(GLIBCXX_CHECK_MATH_DECL, GLIBCXX_CHECK_MATH_DECLS): New.
	* configure: Rebuild.

From-SVN: r279731

From-SVN: r279730

Previously, limited unrolling was enabled at O2 for powerpc in r278034.  At that
time, -fweb and -frename-registers were not enabled together with -funroll-loops
even for -O3.  After that, we notice there are some performance degradations on
SPEC2006fp which caused by without web and rnreg.  This patch enable -fweb
and -frename-registers for -funroll-loops to align original behavior before
r278034.

gcc/
2019-12-23  Jiufu Guo  <guojiufu@linux.ibm.com>

	* config/rs6000/rs6000.c (rs6000_option_override_internal): Enable
	-fweb and -frename-registers with -funroll-loops

From-SVN: r279725