2020-03-16  Vladimir Makarov  <vmakarov@redhat.com>

	PR target/94185
	* lra-spills.c (remove_pseudos): Do not reuse insn alternative
	after changing memory subreg.

2020-03-16  Vladimir Makarov  <vmakarov@redhat.com>

	PR target/94185
	* g++.target/i386/pr94185.C: New test.

Jeff pointed out that using:

   N:  ... /* { dg-error {...} } */
 N+1:      /* { dg-error {...} "" { target *-*-* } .-1 } */

led to two identical test names for line N.  Fixed by adding
a proper test name instead of "".

2020-03-16  Richard Sandiford  <richard.sandiford@arm.com>

gcc/testsuite/
	* gcc.target/aarch64/sve/acle/general-c/sizeless-1.c: Add a test
	name to .-1 dg-error tests.
	* gcc.target/aarch64/sve/acle/general-c/sizeless-2.c: Likewise.

This patch is part of MVE ACLE intrinsics framework.

The patch supports the use of emulation for the single-precision arithmetic
operations for MVE. This changes are to support the MVE ACLE intrinsics which
operates on vector floating point arithmetic operations.

Please refer to Arm reference manual [1] for more details.
[1] https://developer.arm.com/docs/ddi0553/latest

2020-03-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	        Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm.c (arm_libcall_uses_aapcs_base): Modify function to add
	emulator calls for dobule precision arithmetic operations for MVE.

2020-03-16  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/mve_libcall1.c: New test.
	* gcc.target/arm/mve/intrinsics/mve_libcall2.c: Likewise.

This patch is part of MVE ACLE intrinsics framework.
This patches add support to update (read/write) the APSR (Application Program Status Register)
register and FPSCR (Floating-point Status and Control Register) register for MVE.
This patch also enables thumb2 mov RTL patterns for MVE.

A new feature bit vfp_base is added. This bit is enabled for all VFP, MVE and MVE with floating point
extensions. This bit is used to enable the macro TARGET_VFP_BASE. For all the VFP instructions, RTL patterns,
status and control registers are guarded by TARGET_HAVE_FLOAT. But this patch modifies that and the
common instructions, RTL patterns, status and control registers bewteen MVE and VFP are guarded by
TARGET_VFP_BASE macro.

The RTL pattern set_fpscr and get_fpscr are updated to use VFPCC_REGNUM because few MVE intrinsics
set/get carry bit of FPSCR register.

Please refer to Arm reference manual [1] for more details.
[1] https://developer.arm.com/docs/ddi0553/latest

2020-03-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Mihail Ionescu  <mihail.ionescu@arm.com>
	    Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* common/config/arm/arm-common.c (arm_asm_auto_mfpu): When vfp_base
	feature bit is on and -mfpu=auto is passed as compiler option, do not
	generate error on not finding any matching fpu. Because in this case
	fpu is not required.
	* config/arm/arm-cpus.in (vfp_base): Define feature bit, this bit is
	enabled for MVE and also for all VFP extensions.
	(VFPv2): Modify fgroup to enable vfp_base feature bit when ever VFPv2
	is enabled.
	(MVE): Define fgroup to enable feature bits mve, vfp_base and armv7em.
	(MVE_FP): Define fgroup to enable feature bits is fgroup MVE and FPv5
	along with feature bits mve_float.
	(mve): Modify add options in armv8.1-m.main arch for MVE.
	(mve.fp): Modify add options in armv8.1-m.main arch for MVE with
	floating point.
	* config/arm/arm.c (use_return_insn): Replace the
	check with TARGET_VFP_BASE.
	(thumb2_legitimate_index_p): Replace TARGET_HARD_FLOAT with
	TARGET_VFP_BASE.
	(arm_rtx_costs_internal): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE"
	with TARGET_VFP_BASE, to allow cost calculations for copies in MVE as
	well.
	(arm_get_vfp_saved_size): Replace TARGET_HARD_FLOAT with
	TARGET_VFP_BASE, to allow space calculation for VFP registers in MVE
	as well.
	(arm_compute_frame_layout): Likewise.
	(arm_save_coproc_regs): Likewise.
	(arm_fixed_condition_code_regs): Modify to enable using VFPCC_REGNUM
	in MVE as well.
	(arm_hard_regno_mode_ok): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE"
	with equivalent macro TARGET_VFP_BASE.
	(arm_expand_epilogue_apcs_frame): Likewise.
	(arm_expand_epilogue): Likewise.
	(arm_conditional_register_usage): Likewise.
	(arm_declare_function_name): Add check to skip printing .fpu directive
	in assembly file when TARGET_VFP_BASE is enabled and fpu_to_print is
	"softvfp".
	* config/arm/arm.h (TARGET_VFP_BASE): Define.
	* config/arm/arm.md (arch): Add "mve" to arch.
	(eq_attr "arch" "mve"): Enable on TARGET_HAVE_MVE is true.
	(vfp_pop_multiple_with_writeback): Replace "TARGET_HARD_FLOAT
	|| TARGET_HAVE_MVE" with equivalent macro TARGET_VFP_BASE.
	* config/arm/constraints.md (Uf): Define to allow modification to FPCCR
	in MVE.
	* config/arm/thumb2.md (thumb2_movsfcc_soft_insn): Modify target guard
	to not allow for MVE.
	* config/arm/unspecs.md (UNSPEC_GET_FPSCR): Move to volatile unspecs
	enum.
	(VUNSPEC_GET_FPSCR): Define.
	* config/arm/vfp.md (thumb2_movhi_vfp): Add support for VMSR and VMRS
	instructions which move to general-purpose Register from Floating-point
	Special register and vice-versa.
	(thumb2_movhi_fp16): Likewise.
	(thumb2_movsi_vfp): Add support for VMSR and VMRS instructions along
	with MCR and MRC instructions which set and get Floating-point Status
	and Control Register (FPSCR).
	(movdi_vfp): Modify pattern to enable Single-precision scalar float move
	in MVE.
	(thumb2_movdf_vfp): Modify pattern to enable Double-precision scalar
	float move patterns in MVE.
	(thumb2_movsfcc_vfp): Modify pattern to enable single float conditional
	code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check.
	(thumb2_movdfcc_vfp): Modify pattern to enable double float conditional
	code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check.
	(push_multi_vfp): Add support to use VFP VPUSH pattern for MVE by adding
	TARGET_VFP_BASE check.
	(set_fpscr): Add support to set FPSCR register for MVE. Modify pattern
	using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR
	register.
	(get_fpscr): Add support to get FPSCR register for MVE. Modify pattern
		using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR
	register.

2020-03-16  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c: New test.
	* gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c: Likewise.
	* gcc.target/arm/mve/intrinsics/mve_fpu1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/mve_fpu2.c: Likewise.
	* gcc.target/arm/mve/intrinsics/mve_fpu3.c: Likewise.

This patch creates the required framework for MVE ACLE intrinsics.

The following changes are done in this patch to support MVE ACLE intrinsics.

Header file arm_mve.h is added to source code, which contains the definitions of MVE ACLE intrinsics
and different data types used in MVE. Machine description file mve.md is also added which contains the
RTL patterns defined for MVE.

A new reigster "p0" is added which is used in by MVE predicated patterns. A new register class "VPR_REG"
is added and its contents are defined in REG_CLASS_CONTENTS.

The vec-common.md file is modified to support the standard move patterns. The prefix of neon functions
which are also used by MVE is changed from "neon_" to "simd_".
eg: neon_immediate_valid_for_move changed to simd_immediate_valid_for_move.

In the patch standard patterns mve_move, mve_store and move_load for MVE are added and neon.md and vfp.md
files are modified to support this common patterns.

Please refer to Arm reference manual [1] for more details.

[1] https://developer.arm.com/docs/ddi0553/latest

2020-03-06  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Mihail Ionescu  <mihail.ionescu@arm.com>
	    Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config.gcc (arm_mve.h): Include mve intrinsics header file.
	* config/arm/aout.h (p0): Add new register name for MVE predicated
	cases.
	* config/arm-builtins.c (ARM_BUILTIN_SIMD_LANE_CHECK): Define macro
	common to Neon and MVE.
	(ARM_BUILTIN_NEON_LANE_CHECK): Renamed to ARM_BUILTIN_SIMD_LANE_CHECK.
	(arm_init_simd_builtin_types): Disable poly types for MVE.
	(arm_init_neon_builtins): Move a check to arm_init_builtins function.
	(arm_init_builtins): Use ARM_BUILTIN_SIMD_LANE_CHECK instead of
	ARM_BUILTIN_NEON_LANE_CHECK.
	(mve_dereference_pointer): Add function.
	(arm_expand_builtin_args): Call to mve_dereference_pointer when MVE is
	enabled.
	(arm_expand_neon_builtin): Moved to arm_expand_builtin function.
	(arm_expand_builtin): Moved from arm_expand_neon_builtin function.
	* config/arm/arm-c.c (__ARM_FEATURE_MVE): Define macro for MVE and MVE
	with floating point enabled.
	* config/arm/arm-protos.h (neon_immediate_valid_for_move): Renamed to
	simd_immediate_valid_for_move.
	(simd_immediate_valid_for_move): Renamed from
	neon_immediate_valid_for_move function.
	* config/arm/arm.c (arm_options_perform_arch_sanity_checks): Generate
	error if vfpv2 feature bit is disabled and mve feature bit is also
	disabled for HARD_FLOAT_ABI.
	(use_return_insn): Check to not push VFP regs for MVE.
	(aapcs_vfp_allocate): Add MVE check to have same Procedure Call Standard
	as Neon.
	(aapcs_vfp_allocate_return_reg): Likewise.
	(thumb2_legitimate_address_p): Check to return 0 on valid Thumb-2
	address operand for MVE.
	(arm_rtx_costs_internal): MVE check to determine cost of rtx.
	(neon_valid_immediate): Rename to simd_valid_immediate.
	(simd_valid_immediate): Rename from neon_valid_immediate.
	(simd_valid_immediate): MVE check on size of vector is 128 bits.
	(neon_immediate_valid_for_move): Rename to
	simd_immediate_valid_for_move.
	(simd_immediate_valid_for_move): Rename from
	neon_immediate_valid_for_move.
	(neon_immediate_valid_for_logic): Modify call to neon_valid_immediate
	function.
	(neon_make_constant): Modify call to neon_valid_immediate function.
	(neon_vector_mem_operand): Return VFP register for POST_INC or PRE_DEC
	for MVE.
	(output_move_neon): Add MVE check to generate vldm/vstm instrcutions.
	(arm_compute_frame_layout): Calculate space for saved VFP registers for
	MVE.
	(arm_save_coproc_regs): Save coproc registers for MVE.
	(arm_print_operand): Add case 'E' to print memory operands for MVE.
	(arm_print_operand_address): Check to print register number for MVE.
	(arm_hard_regno_mode_ok): Check for arm hard regno mode ok for MVE.
	(arm_modes_tieable_p): Check to allow structure mode for MVE.
	(arm_regno_class): Add VPR_REGNUM check.
	(arm_expand_epilogue_apcs_frame): MVE check to calculate epilogue code
	for APCS frame.
	(arm_expand_epilogue): MVE check for enabling pop instructions in
	epilogue.
	(arm_print_asm_arch_directives): Modify function to disable print of
	.arch_extension "mve" and "fp" for cases where MVE is enabled with
	"SOFT FLOAT ABI".
	(arm_vector_mode_supported_p): Check for modes available in MVE interger
	and MVE floating point.
	(arm_array_mode_supported_p): Add TARGET_HAVE_MVE check for array mode
	pointer support.
	(arm_conditional_register_usage): Enable usage of conditional regsiter
	for MVE.
	(fixed_regs[VPR_REGNUM]): Enable VPR_REG for MVE.
	(arm_declare_function_name): Modify function to disable print of
	.arch_extension "mve" and "fp" for cases where MVE is enabled with
	"SOFT FLOAT ABI".
	* config/arm/arm.h (TARGET_HAVE_MVE): Disable for soft float abi and
	when target general registers are required.
	(TARGET_HAVE_MVE_FLOAT): Likewise.
	(FIXED_REGISTERS): Add bit for VFP_REG class which is enabled in arm.c
	for MVE.
	(CALL_USED_REGISTERS): Set bit for VFP_REG class in CALL_USED_REGISTERS
	which indicate this is not available for across function calls.
	(FIRST_PSEUDO_REGISTER): Modify.
	(VALID_MVE_MODE): Define valid MVE mode.
	(VALID_MVE_SI_MODE): Define valid MVE SI mode.
	(VALID_MVE_SF_MODE): Define valid MVE SF mode.
	(VALID_MVE_STRUCT_MODE): Define valid MVE struct mode.
	(VPR_REGNUM): Add Vector Predication Register in arm_regs_in_sequence
	for MVE.
	(IS_VPR_REGNUM): Macro to check for VPR_REG register.
	(REG_ALLOC_ORDER): Add VPR_REGNUM entry.
	(enum reg_class): Add VPR_REG entry.
	(REG_CLASS_NAMES): Add VPR_REG entry.
	* config/arm/arm.md (VPR_REGNUM): Define.
	(conds): Check is_mve_type attrbiute to differentiate "conditional" and
	"unconditional" instructions.
	(arm_movsf_soft_insn): Modify RTL to not allow for MVE.
	(movdf_soft_insn): Modify RTL to not allow for MVE.
	(vfp_pop_multiple_with_writeback): Enable for MVE.
	(include "mve.md"): Include mve.md file.
	* config/arm/arm_mve.h: Add MVE intrinsics head file.
	* config/arm/constraints.md (Up): Constraint to enable "p0" register in MVE
	for vector predicated operands.
	* config/arm/iterators.md (VNIM1): Define.
	(VNINOTM1): Define.
	(VHFBF_split): Define
	* config/arm/mve.md: New file.
	(mve_mov<mode>): Define RTL for move, store and load in MVE.
	(mve_mov<mode>): Define move RTL pattern with vec_duplicate operator for
	second operand.
	* config/arm/neon.md (neon_immediate_valid_for_move): Rename with
	simd_immediate_valid_for_move.
	(neon_mov<mode>): Split pattern and move expand pattern "movv8hf" which
	is common to MVE and  NEON to vec-common.md file.
	(vec_init<mode><V_elem_l>): Add TARGET_HAVE_MVE check.
	* config/arm/predicates.md (vpr_register_operand): Define.
	* config/arm/t-arm: Add mve.md file.
	* config/arm/types.md (mve_move): Add MVE instructions mve_move to
	attribute "type".
	(mve_store): Add MVE instructions mve_store to attribute "type".
	(mve_load): Add MVE instructions mve_load to attribute "type".
	(is_mve_type): Define attribute.
	* config/arm/vec-common.md (mov<mode>): Modify RTL expand to support
	standard move patterns in MVE along with NEON and IWMMXT with mode
	iterator VNIM1.
	(mov<mode>): Modify RTL expand to support standard move patterns in NEON
	and IWMMXT with mode iterator V8HF.
	(movv8hf): Define RTL expand to support standard "movv8hf" pattern in
	NEON and MVE.
	* config/arm/vfp.md (neon_immediate_valid_for_move): Rename to
	simd_immediate_valid_for_move.

2020-03-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/mve_vector_float.c: New test.
	* gcc.target/arm/mve/intrinsics/mve_vector_float1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/mve_vector_float2.c: Likewise.
	* gcc.target/arm/mve/intrinsics/mve_vector_int.c: Likewise.
	* gcc.target/arm/mve/intrinsics/mve_vector_int1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/mve_vector_int2.c: Likewise.
	* gcc.target/arm/mve/intrinsics/mve_vector_uint.c: Likewise.
	* gcc.target/arm/mve/intrinsics/mve_vector_uint1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/mve_vector_uint2.c: Likewise.
	* gcc.target/arm/mve/mve.exp: New file.
	* lib/target-supports.exp
	(check_effective_target_arm_v8_1m_mve_fp_ok_nocache): Proc to check
	armv8.1-m.main+mve.fp and returning corresponding options.
	(check_effective_target_arm_v8_1m_mve_fp_ok): Proc to call
	check_effective_target_arm_v8_1m_mve_fp_ok_nocache to check support of
	MVE with floating point on the current target.
	(add_options_for_arm_v8_1m_mve_fp): Proc to call
	check_effective_target_arm_v8_1m_mve_fp_ok to return corresponding
	compiler options for MVE with floating point.
	(check_effective_target_arm_v8_1m_mve_ok_nocache): Modify to test and
	return hard float-abi on success.

libphobos/ChangeLog:

2020-03-16  Iain Buclaw  <ibuclaw@gdcproject.org>

	PR d/92792
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* configure.ac (libtool_VERSION): Reset to 1:0:0.
	* libdruntime/Makefile.in: Regenerate.

	* testsuite/20_util/bind/91371.cc: Skip for x32.
	* testsuite/20_util/is_function/91371.cc: Ditto.
	* testsuite/20_util/is_member_function_pointer/91371.cc: Ditto.
	* testsuite/20_util/is_object/91371.cc: Ditto.

There is no need to set mode attribute to XImode since ix86_output_ssemov
can properly encode xmm16-xmm31 registers with and without AVX512VL.

Remove ext_sse_reg_operand since it is no longer needed.

gcc/

	PR target/89229
	* config/i386/i386.md (*movsi_internal): Call ix86_output_ssemov
	for TYPE_SSEMOV.  Remove ext_sse_reg_operand and TARGET_AVX512VL
	check.
	* config/i386/predicates.md (ext_sse_reg_operand): Removed.

gcc/testsuite/

	PR target/89229
	* gcc.target/i386/pr89229-7a.c: New test.
	* gcc.target/i386/pr89229-7b.c: Likewise.
	* gcc.target/i386/pr89229-7c.c: Likewise.

Fixes an ICE in the parser, and deprecates a previously allowed style of
syntax that deviated from GNU-style extended asm.

Reviewed-on: https://github.com/dlang/dmd/pull/10916

gcc/testsuite/ChangeLog:

2020-03-16  Iain Buclaw  <ibuclaw@gdcproject.org>

	* gdc.dg/asm1.d: Add new test for ICE in asm parser.
	* gdc.dg/asm5.d: New test.

Surrounds the gcc-style asm operands with parentheses, as the old style
is now deprecated.

Reviewed-on: https://github.com/dlang/druntime/pull/2986

The following testcase fails with -fcompare-debug.  The problem is that
bar is marked as address_taken only with -g and not without.
I've tracked it down to insert_init_stmt calling gimple_regimplify_operands
even on DEBUG_STMTs.  That function will just insert normal stmts before
the DEBUG_STMT if the DEBUG_STMT operand isn't gimple val or invariant.
While DCE will turn those statements into debug temporaries, it can cause
differences in SSA_NAMEs and more importantly, the ipa references are
generated from those before the DCE happens.
On the testcase, the DEBUG_STMT value is (int)bar.

We could generate DEBUG_STMTs with debug temporaries instead, but I fail to
see the reason to do that, DEBUG_STMTs allow other expressions and all we
want to ensure is that the expressions aren't too large (arbitrarily
complex), but during inlining/function versioning I don't see why something
would queue a DEBUG_STMT with arbitrarily complex expressions in there.

2020-03-16  Jakub Jelinek  <jakub@redhat.com>

	PR debug/94167
	* tree-inline.c (insert_init_stmt): Don't gimple_regimplify_operands
	DEBUG_STMTs.

	* gcc.dg/pr94167.c: New test.

The following testcase fails with -fcompare-debug.  The problem is that
bar is marked as address_taken only with -g and not without.
I've tracked it down to insert_init_stmt calling gimple_regimplify_operands
even on DEBUG_STMTs.  That function will just insert normal stmts before
the DEBUG_STMT if the DEBUG_STMT operand isn't gimple val or invariant.
While DCE will turn those statements into debug temporaries, it can cause
differences in SSA_NAMEs and more importantly, the ipa references are
generated from those before the DCE happens.
On the testcase, the DEBUG_STMT value is (int)bar.

We could generate DEBUG_STMTs with debug temporaries instead, but I fail to
see the reason to do that, DEBUG_STMTs allow other expressions and all we
want to ensure is that the expressions aren't too large (arbitrarily
complex), but during inlining/function versioning I don't see why something
would queue a DEBUG_STMT with arbitrarily complex expressions in there.

2020-03-16  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/94166
	* tree-ssa-reassoc.c (sort_by_mach_mode): Use SSA_NAME_VERSION
	as secondary comparison key.

	* gcc.dg/pr94166.c: New test.

Function loop_distribution::break_alias_scc_partitions needs to compute
SCC with runtime alias edges skipped.  As a result, partitions could be
re-assigned larger post order number than SCC's precedent partition and
distributed before the precedent one.  This fixes the issue by updating
the merged partition to the minimal post order in SCC.

gcc/
    PR tree-optimization/94125
    * tree-loop-distribution.c
    (loop_distribution::break_alias_scc_partitions): Update post order
    number for merged scc.

gcc/testsuite/
    PR tree-optimization/94125
    * gcc.dg/tree-ssa/pr94125.c: New test.

There is no need to set mode attribute to V16SFmode since ix86_output_ssemov
can properly encode xmm16-xmm31 registers with and without AVX512VL.

gcc/

	PR target/89229
	* config/i386/i386.c (ix86_output_ssemov): Handle MODE_SI and
	MODE_SF.
	* config/i386/i386.md (*movsf_internal): Call ix86_output_ssemov
	for TYPE_SSEMOV.  Remove TARGET_PREFER_AVX256, TARGET_AVX512VL
	and ext_sse_reg_operand check.

gcc/testsuite/

	PR target/89229
	* gcc.target/i386/pr89229-6a.c: New test.
	* gcc.target/i386/pr89229-6b.c: Likewise.
	* gcc.target/i386/pr89229-6c.c: Likewise.

Whitespace-only change.

gcc/cp/ChangeLog:

2020-03-15  Iain Sandoe  <iain@sandoe.co.uk>

	* coroutines.cc (co_await_expander): Fix indentation.

Addresses issues where the two-column format of options descriptions was
used, but the columns were separated by spaces rather than a single tab,
causing the help output to be more verbose than intended.

gcc/ChangeLog:

2020-03-15  Lewis Hyatt  <lhyatt@gmail.com>

	* common.opt: Avoid redundancy in the help text.
	* config/arc/arc.opt: Likewise.
	* config/cr16/cr16.opt: Likewise.

gcc/c-family/ChangeLog:

2020-03-15  Lewis Hyatt  <lhyatt@gmail.com>

	* c.opt: Avoid redundancy in the help text.

gcc/fortran/ChangeLog:

2020-03-15  Lewis Hyatt  <lhyatt@gmail.com>

	* lang.opt: Avoid redundancy in the help text.

gcc/testsuite/ChangeLog:

2020-03-15  Lewis Hyatt  <lhyatt@gmail.com>

	* gcc.misc-tests/help.exp: Adapt to new output for
	-Walloc-size-larger-than= option.

tree-nested.c didn't handle C array sections in {,task_,in_}reduction clauses.

2020-03-14  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/93566
	* tree-nested.c (convert_nonlocal_omp_clauses,
	convert_local_omp_clauses): Handle {,in_,task_}reduction clauses
	with C/C++ array sections.

	* testsuite/libgomp.c/pr93566.c: New test.

There is no need to set mode attribute to XImode since ix86_output_ssemov
can properly encode xmm16-xmm31 registers with and without AVX512VL.

gcc/

	PR target/89229
	* config/i386/i386.md (*movdi_internal): Call ix86_output_ssemov
	for TYPE_SSEMOV.  Remove ext_sse_reg_operand and TARGET_AVX512VL
	check.

gcc/testsuite/

	PR target/89229
	* gcc.target/i386/pr89229-5a.c: New test.
	* gcc.target/i386/pr89229-5b.c: Likewise.
	* gcc.target/i386/pr89229-5c.c: Likewise.

Here the template arguments for the partial specialization are valid
arguments for the template, but not for a partial specialization, because
'd' can never be deduced to anything other than an empty pack.

gcc/cp/ChangeLog
2020-03-14  Jason Merrill  <jason@redhat.com>

	PR c++/92068
	* pt.c (process_partial_specialization): Error rather than crash on
	extra pack expansion.

find_parameter_packs_r doesn't look through typedefs, which is normally
correct, but that means we need to handle their declarations specially.

gcc/cp/ChangeLog
2020-03-14  Jason Merrill  <jason@redhat.com>

	PR c++/92909
	* pt.c (find_parameter_packs_r): [DECL_EXPR]: Walk
	DECL_ORIGINAL_TYPE of a typedef.

When cp_unevaluated_operand is set, tsubst_decl thinks that if it sees a
PARM_DECL that isn't already in local_specializations, we're in a decltype
in a trailing return type or some such, and so we only want a substitution
for a single PARM_DECL.  In this case, we want the whole chain, so make sure
cp_unevaluated_operand is cleared.

gcc/cp/ChangeLog
2020-03-14  Jason Merrill  <jason@redhat.com>

	PR c++/93248
	* pt.c (build_deduction_guide): Clear cp_unevaluated_operand for
	substituting DECL_ARGUMENTS.

Includes port fixes for Musl on ARM, AArch64, and SystemZ targets.

Reviewed-on: https://github.com/dlang/druntime/pull/2751
             https://github.com/dlang/druntime/pull/2843
             https://github.com/dlang/druntime/pull/2844
             https://github.com/dlang/druntime/pull/2898

Run tests should use vmx_hw, not just powerpc_altivec_ok.

gcc/testsuite/
	PR target/94176
	* gcc.target/powerpc/fold-vec-mule-misc.c: Use vmx_hw selector.

2020-03-14  Jakub Jelinek  <jakub@redhat.com>

	* gimple-fold.c (gimple_fold_builtin_strncpy): Change
	"a an" to "an" in a comment.
	* hsa-common.h (is_a_helper): Likewise.
	* tree-ssa-strlen.c (maybe_diag_stxncpy_trunc): Likewise.
	* config/arc/arc.c (arc600_corereg_hazard): Likewise.
	* config/s390/s390.c (s390_indirect_branch_via_thunk): Likewise.

	* logic.cc (formula::formula): Change "a an" to "an" in a comment.
	* parser.c (cp_debug_parser): Change "a an" to "an" in a string
	literal.

2020-03-13  Aaron Sawdey  <acsawdey@linux.ibm.com>

	PR target/92379
	* config/rs6000/rs6000.c (num_insns_constant_multi) Don't shift a
	64-bit value by 64 bits (UB).

PR analyzer/94099 and PR analyzer/94105 both report ICEs relating to
calling region_model::get_lvalue on a NOP_EXPR.

PR analyzer/94099's ICE happens when generating a checker_path when
encountering an unhandled tree code (NOP_EXPR) in get_lvalue with a
NULL context (from for_each_state_change).

PR analyzer/94105 ICE happens when handling an ARRAY_REF where the
first operand is a NOP_EXPR: the unhandled tree code gives us
a symbolic_region, but the case for ARRAY_REF assumes we have an
array_region.

This patch fixes the ICEs by handling NOP_EXPR within
region_model::get_lvalue, and bulletproofs both of the above sources
of failure.

gcc/analyzer/ChangeLog:
	PR analyzer/94099
	PR analyzer/94105
	* diagnostic-manager.cc (for_each_state_change): Bulletproof
	against errors in get_rvalue by passing a
	tentative_region_model_context and rejecting if there's an error.
	* region-model.cc (region_model::get_lvalue_1): When handling
	ARRAY_REF, handle results of error-handling.  Handle NOP_EXPR.

gcc/testsuite/ChangeLog:
	PR analyzer/94099
	PR analyzer/94105
	* gcc.dg/analyzer/pr94099.c: New test.
	* gcc.dg/analyzer/pr94105.c: New test.

1. Implement DIP 1010 - (Static foreach)

Support for 'static foreach' has been added.  'static foreach' is a conditional
compilation construct that is to 'foreach' what 'static if' is to 'if'.  It is
a convenient way to generate declarations and statements by iteration.

    import std.conv: to;

    static foreach(i; 0 .. 10)
    {

        // a 'static foreach' body does not introduce a nested scope
        // (similar to 'static if').

        // The following mixin declaration is at module scope:
        // declares 10 variables x0, x1, ..., x9
        mixin('enum x' ~ to!string(i) ~ ' = i;');
    }

    import std.range: iota;
    // all aggregate types that can be iterated with a standard 'foreach'
    // loop are also supported by static foreach:
    static foreach(i; iota(10))
    {
        // we access the declarations generated in the first 'static foreach'
        pragma(msg, "x", i, ": ", mixin(`x` ~ to!string(i)));
        static assert(mixin(`x` ~ to!string(i)) == i);
    }

    void main()
    {
        import std.conv: text;
        import std.typecons: tuple;
        import std.algorithm: map;
        import std.stdio: writeln;

        // 'static foreach' has both declaration and statement forms
        // (similar to 'static if').

        static foreach(x; iota(3).map!(i => tuple(text("x", i), i)))
        {
            // generates three local variables x0, x1 and x2.
            mixin(text(`int `,x[0],` = x[1];`));

            scope(exit) // this is within the scope of 'main'
            {
                writeln(mixin(x[0]));
            }
        }

        writeln(x0," ",x1," ",x2); // first runtime output
    }

2. Aliases can be created directly from a '__trait'.

Aliases can be created directly from the traits that return symbol(s) or
tuples.  This includes 'getMember', 'allMembers', 'derivedMembers', 'parent',
'getOverloads', 'getVirtualFunctions', 'getVirtualMethods', 'getUnitTests',
'getAttributes' and finally 'getAliasThis'.  Previously an 'AliasSeq' was
necessary in order to alias their return.  Now the grammar allows to write
shorter declarations:

    struct Foo
    {
        static int a;
    }

    alias oldWay = AliasSeq!(__traits(getMember, Foo, "a"))[0];
    alias newWay = __traits(getMember, Foo, "a");

To permit this it was more interesting to include '__trait' in the basic types
rather than just changing the alias syntax. So additionally, wherever a type
appears a '__trait' can be used, for example in a variable declaration:

    struct Foo { static struct Bar {} }
    const(__traits(getMember, Foo, "Bar")) fooBar;
    static assert(is(typeof(fooBar) == const(Foo.Bar)));

3. fix Issue 10100 - Identifiers with double underscores and allMembers

The identifer whitelist has been converted into a blacklist of all possible
internal D language declarations.

Reviewed-on: https://github.com/dlang/dmd/pull/10791

2020-03-13  Vasee Vinayagamoorthy  <vaseeharan.vinayagamoorthy@arm.com>

gcc/testsuite/
	* gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c: Fix DejaGnu
	typo.

2020-03-13  Vladimir Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/92303
	* lra-spills.c (remove_pseudos): Try to simplify memory subreg.

gcc/testsuite/ChangeLog:

       * gcc.dg/torture/pr54261-1.c: Correct built-in declartion.

gcc/c/ChangeLog:

	PR c/94040
	* c-decl.c (builtin_structptr_type_count): New constant.
	(match_builtin_function_types): Reject decls that are incompatible
	in types pointed to by pointers.
	(diagnose_mismatched_decls): Adjust comments.

gcc/testsuite/ChangeLog:

	PR c/94040
	* gcc.dg/Wbuiltin-declaration-mismatch-12.c: Relax test to look
	for warning name rather than the exact text.
	* gcc.dg/Wbuiltin-declaration-mismatch-14.c: New test.
	* gcc.dg/Wbuiltin-declaration-mismatch-15.c: New test.
	* gcc.dg/pr62090.c: Prune expected warning.
	* gcc.dg/pr89314.c: Look for warning name rather than text.

	* gcc.target/i386/pr64409.c: Do not limit compilation to x32 targets.
	(dg-error): Quote 'ms_abi' attribute.
	* gcc.target/i386/pr71958.c: Do not limit compilation to x32 targets.
	Require maybe_x32 effective target.
	(dg-options): Add -mx32.
	(dg-error): Quote 'ms_abi' attribute.
	* gcc.target/i386/pr90096.c (dg-error): Update relative
	location of target x32 error.

The df dataflow solvers use the aux field in the basic_block struct,
although that is reserved for any use by passes.  And not only that,
it is required that you set all such fields to NULL before calling
the solvers, or you quietly get wrong results.

This changes the solvers to use a local array for last_change_age
instead, just like it already had a local array for last_visit_age.

	PR rtl-optimization/94148
	PR rtl-optimization/94042
	* df-core.c (BB_LAST_CHANGE_AGE): Delete.
	(df_worklist_propagate_forward): New parameter last_change_age, use
	that instead of bb->aux.
	(df_worklist_propagate_backward): Ditto.
	(df_worklist_dataflow_doublequeue): Use a local array last_change_age.

In build_over_call, we are emitting a redundant -Wdeprecated-declarations
warning about the deprecated callee function, first from mark_used and again
from build_addr_func <- decay_conversion <- cp_build_addr_expr <- mark_used.

It seems this second deprecation warning coming from build_addr_func will always
be redundant, so we can safely use a warning_sentinel to disable it before
calling build_addr_func.  (And any deprecation warning that could come from
build_addr_func would be for FN, so we wouldn't be suppressing too much.)

gcc/cp/ChangeLog:

	PR c++/67960
	* call.c (build_over_call): Use a warning_sentinel to disable
	warn_deprecated_decl before calling build_addr_func.

gcc/testsuite/ChangeLog:

	PR c++/67960
	* g++.dg/diagnostic/pr67960.C: New test.
	* g++.dg/diagnostic/pr67960-2.C: New test.

This avoids HWI -> unsigned truncation to end up with zero alignment
which set_ptr_info_alignment ICEs on.

2020-03-13  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/94163
	* tree-ssa-pre.c (create_expression_by_pieces): Check
	whether alignment would be zero.