This removes support for EOL versions of NetBSD and syncs the
definitions with patches from NetBSD upstream.

The only change here that isn't from upstream is to use _CTYPE_BL for
the isblank class, which is correct but wasn't previously done either in
FSF GCC or the NetBSD packages.

2020-01-16  Kai-Uwe Eckhardt  <kuehro@gmx.de>
	    Matthew Bauer  <mjbauer95@gmail.com>
	    Jonathan Wakely  <jwakely@redhat.com>

	PR bootstrap/64271 (partial)
	* config/os/bsd/netbsd/ctype_base.h (ctype_base::mask): Change type
	to unsigned short.
	(ctype_base::alpha, ctype_base::digit, ctype_base::xdigit)
	(ctype_base::print, ctype_base::graph, ctype_base::alnum): Sync
	definitions with NetBSD upstream.
	(ctype_base::blank): Use _CTYPE_BL.
	* config/os/bsd/netbsd/ctype_configure_char.cc (_C_ctype_): Remove
	Declaration.
	(ctype<char>::classic_table): Use _C_ctype_tab_ instead of _C_ctype_.
	(ctype<char>::do_toupper, ctype<char>::do_tolower): Cast char
	parameters to unsigned char.
	* config/os/bsd/netbsd/ctype_inline.h (ctype<char>::is): Likewise.

gcc/ChangeLog:

2020-01-16  Stam Markianos-Wright  <stam.markianos-wright@arm.com>

	* config/arm/arm.c
	(arm_invalid_conversion): New function for target hook.
	(arm_invalid_unary_op): New function for target hook.
	(arm_invalid_binary_op): New function for target hook.

gcc/testsuite/ChangeLog:

2020-01-16  Stam Markianos-Wright  <stam.markianos-wright@arm.com>

	* g++.target/arm/bfloat_cpp_typecheck.C: New test.
	* gcc.target/arm/bfloat16_scalar_typecheck.c: New test.
	* gcc.target/arm/bfloat16_vector_typecheck_1.c: New test.
	* gcc.target/arm/bfloat16_vector_typecheck_2.c: New test.

gcc/ChangeLog:

2020-01-16  Stam Markianos-Wright  <stam.markianos-wright@arm.com>

	* config.gcc: Add arm_bf16.h.
	* config/arm/arm-builtins.c (arm_mangle_builtin_type): Fix comment.
	(arm_simd_builtin_std_type): Add BFmode.
	(arm_init_simd_builtin_types): Define element types for vector types.
	(arm_init_bf16_types): New function.
	(arm_init_builtins): Add arm_init_bf16_types function call.
	* config/arm/arm-modes.def: Add BFmode and V4BF, V8BF vector modes.
	* config/arm/arm-simd-builtin-types.def: Add V4BF, V8BF.
	* config/arm/arm.c (aapcs_vfp_sub_candidate):  Add BFmode.
	(arm_hard_regno_mode_ok): Add BFmode and tidy up statements.
	(arm_vector_mode_supported_p): Add V4BF, V8BF.
	(arm_mangle_type):  Add __bf16.
	* config/arm/arm.h: Add V4BF, V8BF to VALID_NEON_DREG_MODE,
	VALID_NEON_QREG_MODE respectively. Add export arm_bf16_type_node,
	arm_bf16_ptr_type_node.
	* config/arm/arm.md: Add BFmode to movhf expand, mov pattern and
	define_split between ARM registers.
	* config/arm/arm_bf16.h: New file.
	* config/arm/arm_neon.h: Add arm_bf16.h and Bfloat vector types.
	* config/arm/iterators.md: (ANY64_BF, VDXMOV, VHFBF, HFBF, fporbf): New.
	(VQXMOV): Add V8BF.
	* config/arm/neon.md: Add BF vector types to movhf NEON move patterns.
	* config/arm/vfp.md: Add BFmode to movhf patterns.

gcc/testsuite/ChangeLog:

2020-01-16  Stam Markianos-Wright  <stam.markianos-wright@arm.com>

	* g++.dg/abi/mangle-neon.C: Add BF16 SIMD types.
	* g++.dg/ext/arm-bf16/bf16-mangle-1.C: New test.
	* gcc.target/arm/bfloat16_scalar_1_1.c: New test.
	* gcc.target/arm/bfloat16_scalar_1_2.c: New test.
	* gcc.target/arm/bfloat16_scalar_2_1.c: New test.
	* gcc.target/arm/bfloat16_scalar_2_2.c: New test.
	* gcc.target/arm/bfloat16_scalar_3_1.c: New test.
	* gcc.target/arm/bfloat16_scalar_3_2.c: New test.
	* gcc.target/arm/bfloat16_scalar_4.c: New test.
	* gcc.target/arm/bfloat16_simd_1_1.c: New test.
	* gcc.target/arm/bfloat16_simd_1_2.c: New test.
	* gcc.target/arm/bfloat16_simd_2_1.c: New test.
	* gcc.target/arm/bfloat16_simd_2_2.c: New test.
	* gcc.target/arm/bfloat16_simd_3_1.c: New test.
	* gcc.target/arm/bfloat16_simd_3_2.c: New test.

gcc/ChangeLog:

2020-01-16  Mihail Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/arm/arm-cpus.in (mve, mve_float): New features.
	(dsp, mve, mve.fp): New options.
	* config/arm/arm.h (TARGET_HAVE_MVE, TARGET_HAVE_MVE_FLOAT): Define.
	* config/arm/t-rmprofile: Map v8.1-M multilibs to v8-M.
	* doc/invoke.texi: Document the armv8.1-m mve and dps options.

gcc/testsuite/ChangeLog:

2020-01-16  Mihail Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* testsuite/gcc.target/arm/multilib.exp: Add v8.1-M entries.

The patch is straightforward: it redefines ARMv8_1m_main as having the
same features as ARMv8m_main (and thus as having the cmse feature) with
the extra features represented by armv8_1m_main.  It also removes the
error for using -mcmse on Armv8.1-M Mainline.

*** gcc/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm-cpus.in (ARMv8_1m_main): Redefine as an extension to
	Armv8-M Mainline.
	* config/arm/arm.c (arm_options_perform_arch_sanity_checks): Remove
	error for using -mcmse when targeting Armv8.1-M Mainline.

This change to use BLXNS to call a nonsecure function from secure
directly (not using a libcall) is made in 2 steps:
- change nonsecure_call patterns to use blxns instead of calling
  __gnu_cmse_nonsecure_call
- loosen requirement for function address to allow any register when
  doing BLXNS.

The former is a straightforward check over whether instructions added in
Armv8.1-M Mainline are available while the latter consist in making the
nonsecure call pattern accept any register by using match_operand and
changing the nonsecure_call_internal expander to no force r4 when
targeting Armv8.1-M Mainline.

The tricky bit is actually in the test update, specifically how to check
that register lists for CLRM have all registers except for the one
holding parameters (already done) and the one holding the address used
by BLXNS. This is achieved with 3 scan-assembler directives.

1) The first one lists all registers that can appear in CLRM but make
   each of them optional.
   Property guaranteed: no wrong register is cleared and none appears
   twice in the register list.
2) The second directive check that the CLRM is made of a fixed number
   of the right registers to be cleared. The number used is the number
   of registers that could contain a secret minus one (used to hold the
   address of the function to call.
   Property guaranteed: register list has the right number of registers
   Cumulated property guaranteed: only registers with a potential secret
   are cleared and they are all listed but ont
3) The last directive checks that we cannot find a CLRM with a register
   in it that also appears in BLXNS. This is check via the use of a
   back-reference on any of the allowed register in CLRM, the
   back-reference enforcing that whatever register match in CLRM must be
   the same in the BLXNS.
   Property guaranteed: register used for BLXNS is different from
   registers cleared in CLRM.

Some more care needs to happen for the gcc.target/arm/cmse/cmse-1.c
testcase due to there being two CLRM generated. To ensure the third
directive match the right CLRM to the BLXNS, a negative lookahead is
used between the CLRM register list and the BLXNS. The way negative
lookahead work is by matching the *position* where a given regular
expression does not match. In this case, since it comes after the CLRM
register list it is requesting that what comes after the register list
does not have a CLRM again followed by BLXNS. This guarantees that the
.*blxns after only matches a blxns without another CLRM before.

*** gcc/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm.md (nonsecure_call_internal): Do not force memory
	address in r4 when targeting Armv8.1-M Mainline.
	(nonsecure_call_value_internal): Likewise.
	* config/arm/thumb2.md (nonsecure_call_reg_thumb2): Make memory address
	a register match_operand again.  Emit BLXNS when targeting
	Armv8.1-M Mainline.
	(nonsecure_call_value_reg_thumb2): Likewise.

*** gcc/testsuite/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* gcc.target/arm/cmse/cmse-1.c: Add check for BLXNS when instructions
	introduced in Armv8.1-M Mainline Security Extensions are available and
	restrict checks for libcall to __gnu_cmse_nonsecure_call to Armv8-M
	targets only.  Adapt CLRM check to verify register used for BLXNS is
	not in the CLRM register list.
	* gcc.target/arm/cmse/cmse-14.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c: Likewise and adapt
	check for LSB clearing bit to be using the same register as BLXNS when
	targeting Armv8.1-M Mainline.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-5.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-7.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-9.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-and-union.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/union-1.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/union-2.c: Likewise.
	* gcc.target/arm/cmse/cmse-15.c: Count BLXNS when targeting Armv8.1-M
	Mainline and restrict libcall count to Armv8-M.

This patch adds two new patterns for the VLSTM and VLLDM instructions.
cmse_nonsecure_call_inline_register_clear is then modified to
generate VLSTM and VLLDM respectively before and after calls to
functions with the cmse_nonsecure_call attribute in order to have lazy
saving, clearing and restoring of VFP registers. Since these
instructions do not do writeback of the base register, the stack is adjusted
prior the lazy store and after the lazy load with appropriate frame
debug notes to describe the effect on the CFA register.

As with CLRM, VSCCLRM and VSTR/VLDR, the instruction is modeled as an
unspecified operation to the memory pointed to by the base register.

*** gcc/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm.c (arm_add_cfa_adjust_cfa_note): Declare early.
	(cmse_nonsecure_call_inline_register_clear): Define new lazy_fpclear
	variable as true when floating-point ABI is not hard.  Replace
	check against TARGET_HARD_FLOAT_ABI by checks against lazy_fpclear.
	Generate VLSTM and VLLDM instruction respectively before and
	after a function call to cmse_nonsecure_call function.
	* config/arm/unspecs.md (VUNSPEC_VLSTM): Define unspec.
	(VUNSPEC_VLLDM): Likewise.
	* config/arm/vfp.md (lazy_store_multiple_insn): New define_insn.
	(lazy_load_multiple_insn): Likewise.

*** gcc/testsuite/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13.c: Add check for VLSTM and
	VLLDM.
	* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8.c: Likewise.

The patch is fairly straightforward in its approach and consist of the
following 3 logical changes:
- abstract the number of floating-point register to clear in
  max_fp_regno
- use max_fp_regno to decide how many registers to clear so that the
  same code works for Armv8-M and Armv8.1-M Mainline
- emit vpush and vpop instruction respectively before and after a
  nonsecure call

Note that as in the patch to clear GPRs inline, debug information has to
be disabled for VPUSH and VPOP due to VPOP adding CFA adjustment note
for SP when R7 is sometimes used as CFA.

ChangeLog entries are as follows:

*** gcc/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm.c (vfp_emit_fstmd): Declare early.
	(arm_emit_vfp_multi_reg_pop): Likewise.
	(cmse_nonsecure_call_inline_register_clear): Abstract number of VFP
	registers to clear in max_fp_regno.  Emit VPUSH and VPOP to save and
	restore callee-saved VFP registers.

*** gcc/testsuite/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c: Add check for
	VPUSH and VPOP and update expectation for VSCCLRM.
	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c: Likewise.

Besides changing the set of registers that needs to be cleared inline,
this patch also generates the push and pop to save and restore
callee-saved registers without trusting the callee inline. To make the
code more future-proof, this (currently) Armv8.1-M specific behavior is
expressed in terms of clearing of callee-saved registers rather than
directly based on the targets.

The patch contains 1 subtlety:

Debug information is disabled for push and pop because the
REG_CFA_RESTORE notes used to describe popping of registers do not stack.
Instead, they just reset the debug state for the register to the one at
the beginning of the function, which is incorrect for a register that is
pushed twice (in prologue and before nonsecure call) and then popped for
the first time. In particular, this occasionally trips CFI note creation
code when there are two codepaths to the epilogue, one of which does not
go through the nonsecure call. Obviously this mean that debugging
between the push and pop is not reliable.

*** gcc/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm.c (arm_emit_multi_reg_pop): Declare early.
	(cmse_nonsecure_call_clear_caller_saved): Rename into ...
	(cmse_nonsecure_call_inline_register_clear): This.  Save and clear
	callee-saved GPRs as well as clear ip register before doing a nonsecure
	call then restore callee-saved GPRs after it when targeting
	Armv8.1-M Mainline.
	(arm_reorg): Adapt to function rename.

*** gcc/testsuite/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* gcc.target/arm/cmse/cmse-1.c: Add check for PUSH and POP and update
	CLRM check.
	* gcc.target/arm/cmse/cmse-14.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-5.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-7.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-9.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-and-union.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/soft-sp/cmse-7.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/soft-sp/cmse-8.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/softfp/union-1.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/softfp/union-2.c: Likewise.

This patch adds a new pattern for the VSCCLRM instruction.
cmse_clear_registers () is then modified to use the new VSCCLRM
instruction when targeting Armv8.1-M Mainline, thus, making the Armv8-M
register clearing code specific to Armv8-M.

Since the VSCCLRM instruction mandates VPR in the register list, the
pattern is encoded with a parallel which only requires an unspecified
VUNSPEC_CLRM_VPR constant modelling the APSR clearing. Other expression
in the parallel are expected to be set expression for clearing the VFP
registers.

*** gcc/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm-protos.h (clear_operation_p): Adapt prototype.
	* config/arm/arm.c (clear_operation_p): Extend to be able to check a
	clear_vfp_multiple pattern based on a new vfp parameter.
	(cmse_clear_registers): Generate VSCCLRM to clear VFP registers when
	targeting Armv8.1-M Mainline.
	(cmse_nonsecure_entry_clear_before_return): Clear VFP registers
	unconditionally when targeting Armv8.1-M Mainline architecture.  Check
	whether VFP registers are available before looking call_used_regs for a
	VFP register.
	* config/arm/predicates.md (clear_multiple_operation): Adapt to change
	of prototype of clear_operation_p.
	(clear_vfp_multiple_operation): New predicate.
	* config/arm/unspecs.md (VUNSPEC_VSCCLRM_VPR): New volatile unspec.
	* config/arm/vfp.md (clear_vfp_multiple): New define_insn.

*** gcc/testsuite/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* gcc.target/arm/cmse/bitfield-1.c: Add check for VSCCLRM.
	* gcc.target/arm/cmse/bitfield-2.c: Likewise.
	* gcc.target/arm/cmse/bitfield-3.c: Likewise.
	* gcc.target/arm/cmse/cmse-1.c: Likewise.
	* gcc.target/arm/cmse/struct-1.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-5.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-5.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-5.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-5.c: Likewise.

This patch adds a new pattern for the CLRM instruction and guards the
current clearing code in output_return_instruction() and thumb_exit()
on Armv8.1-M Mainline instructions not being present.
cmse_clear_registers () is then modified to use the new CLRM instruction
when targeting Armv8.1-M Mainline while keeping Armv8-M register
clearing code for VFP registers.

For the CLRM instruction, which does not mandated APSR in the register
list, checking whether it is the right volatile unspec or a clearing
register is done in clear_operation_p.

Note that load/store multiple were deemed sufficiently different in
terms of RTX structure compared to the CLRM pattern for a different
function to be used to validate the match_parallel.

ChangeLog entries are as follows:

*** gcc/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm-protos.h (clear_operation_p): Declare.
	* config/arm/arm.c (clear_operation_p): New function.
	(cmse_clear_registers): Generate clear_multiple instruction pattern if
	targeting Armv8.1-M Mainline or successor.
	(output_return_instruction): Only output APSR register clearing if
	Armv8.1-M Mainline instructions not available.
	(thumb_exit): Likewise.
	* config/arm/predicates.md (clear_multiple_operation): New predicate.
	* config/arm/thumb2.md (clear_apsr): New define_insn.
	(clear_multiple): Likewise.
	* config/arm/unspecs.md (VUNSPEC_CLRM_APSR): New volatile unspec.

*** gcc/testsuite/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* gcc.target/arm/cmse/bitfield-1.c: Add check for CLRM.
	* gcc.target/arm/cmse/bitfield-2.c: Likewise.
	* gcc.target/arm/cmse/bitfield-3.c: Likewise.
	* gcc.target/arm/cmse/struct-1.c: Likewise.
	* gcc.target/arm/cmse/cmse-14.c: Likewise.
	* gcc.target/arm/cmse/cmse-1.c: Likewise.  Restrict checks for Armv8-M
	GPR clearing when CLRM is not available.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-5.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-7.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-9.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-5.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-5.c: likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c: likewise.
	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c: likewise.
	* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-5.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-5.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/union-1.c: Likewise.
	* gcc.target/arm/cmse/mainline/8_1m/union-2.c: Likewise.

This patch consists mainly of creating 2 new instruction patterns to
push and pop special FP registers via vldm and vstr and using them in
prologue and epilogue. The patterns are defined as push/pop with an
unspecified operation on the memory accessed, with an unspecified
constant indicating what special FP register is being saved/restored.

Other aspects of the patch include:
  * defining the set of special registers that can be saved/restored and
    their name
  * reserving space in the stack frames for these push/pop
  * preventing return via pop
  * guarding the clearing of FPSCR to target architecture not having
    Armv8.1-M Mainline instructions.

*** gcc/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm.c (fp_sysreg_names): Declare and define.
	(use_return_insn): Also return false for Armv8.1-M Mainline.
	(output_return_instruction): Skip FPSCR clearing if Armv8.1-M
	Mainline instructions are available.
	(arm_compute_frame_layout): Allocate space in frame for FPCXTNS
	when targeting Armv8.1-M Mainline Security Extensions.
	(arm_expand_prologue): Save FPCXTNS if this is an Armv8.1-M
	Mainline entry function.
	(cmse_nonsecure_entry_clear_before_return): Clear IP and r4 if
	targeting Armv8.1-M Mainline or successor.
	(arm_expand_epilogue): Fix indentation of caller-saved register
	clearing.  Restore FPCXTNS if this is an Armv8.1-M Mainline
	entry function.
	* config/arm/arm.h (TARGET_HAVE_FP_CMSE): New macro.
	(FP_SYSREGS): Likewise.
	(enum vfp_sysregs_encoding): Define enum.
	(fp_sysreg_names): Declare.
	* config/arm/unspecs.md (VUNSPEC_VSTR_VLDR): New volatile unspec.
	* config/arm/vfp.md (push_fpsysreg_insn): New define_insn.
	(pop_fpsysreg_insn): Likewise.

*** gcc/testsuite/Changelog ***

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* gcc.target/arm/cmse/bitfield-1.c: add checks for VSTR and VLDR.
	* gcc.target/arm/cmse/bitfield-2.c: Likewise.
	* gcc.target/arm/cmse/bitfield-3.c: Likewise.
	* gcc.target/arm/cmse/cmse-1.c: Likewise.
	* gcc.target/arm/cmse/struct-1.c: Likewise.
	* gcc.target/arm/cmse/cmse.exp: Run existing Armv8-M Mainline tests
	from mainline/8m subdirectory and new Armv8.1-M Mainline tests from
	mainline/8_1m subdirectory.
	* gcc.target/arm/cmse/mainline/bitfield-4.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/bitfield-4.c: This.
	* gcc.target/arm/cmse/mainline/bitfield-5.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/bitfield-5.c: This.
	* gcc.target/arm/cmse/mainline/bitfield-6.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/bitfield-6.c: This.
	* gcc.target/arm/cmse/mainline/bitfield-7.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/bitfield-7.c: This.
	* gcc.target/arm/cmse/mainline/bitfield-8.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/bitfield-8.c: This.
	* gcc.target/arm/cmse/mainline/bitfield-9.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/bitfield-9.c: This.
	* gcc.target/arm/cmse/mainline/bitfield-and-union-1.c: Move and rename
	into ...
	* gcc.target/arm/cmse/mainline/8m/bitfield-and-union.c: This.
	* gcc.target/arm/cmse/mainline/hard-sp/cmse-13.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-13.c: This.  Clean up
	dg-skip-if directive for float ABI.
	* gcc.target/arm/cmse/mainline/hard-sp/cmse-5.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-5.c: This.  Clean up
	dg-skip-if directive for float ABI.
	* gcc.target/arm/cmse/mainline/hard-sp/cmse-7.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-7.c: This.  Clean up
	dg-skip-if directive for float ABI.
	* gcc.target/arm/cmse/mainline/hard-sp/cmse-8.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-8.c: This.  Clean up
	dg-skip-if directive for float ABI.
	* gcc.target/arm/cmse/mainline/hard/cmse-13.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/hard/cmse-13.c: This.  Clean up
	dg-skip-if directive for float ABI.
	* gcc.target/arm/cmse/mainline/hard/cmse-5.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/hard/cmse-5.c: This.  Clean up
	dg-skip-if directive for float ABI.
	* gcc.target/arm/cmse/mainline/hard/cmse-7.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/hard/cmse-7.c: This.  Clean up
	dg-skip-if directive for float ABI.
	* gcc.target/arm/cmse/mainline/hard/cmse-8.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/hard/cmse-8.c: This.  Clean up
	dg-skip-if directive for float ABI.
	* gcc.target/arm/cmse/mainline/soft/cmse-13.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/soft/cmse-13.c: This.  Clean up
	dg-skip-if directive for float ABI.
	* gcc.target/arm/cmse/mainline/soft/cmse-5.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/soft/cmse-5.c: This.  Clean up
	dg-skip-if directive for float ABI.
	* gcc.target/arm/cmse/mainline/soft/cmse-7.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/soft/cmse-7.c: This.  Clean up
	dg-skip-if directive for float ABI.
	* gcc.target/arm/cmse/mainline/soft/cmse-8.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/soft/cmse-8.c: This.  Clean up
	dg-skip-if directive for float ABI.
	* gcc.target/arm/cmse/mainline/softfp-sp/cmse-5.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-5.c: This.  Clean up
	dg-skip-if directive for float ABI.
	* gcc.target/arm/cmse/mainline/softfp-sp/cmse-7.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-7.c: This.  Clean up
	dg-skip-if directive for float ABI.
	* gcc.target/arm/cmse/mainline/softfp-sp/cmse-8.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-8.c: This.  Clean up
	dg-skip-if directive for float ABI.
	* gcc.target/arm/cmse/mainline/softfp/cmse-13.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/softfp/cmse-13.c: This.  Clean up
	dg-skip-if directive for float ABI.
	* gcc.target/arm/cmse/mainline/softfp/cmse-5.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/softfp/cmse-5.c: This.  Clean up
	dg-skip-if directive for float ABI.
	* gcc.target/arm/cmse/mainline/softfp/cmse-7.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/softfp/cmse-7.c: This.  Clean up
	dg-skip-if directive for float ABI.
	* gcc.target/arm/cmse/mainline/softfp/cmse-8.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/softfp/cmse-8.c: This.  Clean up
	dg-skip-if directive for float ABI.
	* gcc.target/arm/cmse/mainline/union-1.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/union-1.c: This.
	* gcc.target/arm/cmse/mainline/union-2.c: Move into ...
	* gcc.target/arm/cmse/mainline/8m/union-2.c: This.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-5.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-7.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-9.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/bitfield-and-union.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-5.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-5.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-5.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-5.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/union-1.c: New file.
	* gcc.target/arm/cmse/mainline/8_1m/union-2.c: New file.
	* lib/target-supports.exp (check_effective_target_arm_cmse_clear_ok):
	New procedure.

Besides the expected enabling of the new value for the -march
command-line option (-march=armv8.1-m.main) and its extensions (see
below), this patch disables support of the Security Extensions for this
newly added architecture. This is done both by not including the cmse
bit in the architecture description and by throwing an error message
when user request Armv8.1-M Mainline Security Extensions. Note that
Armv8-M Baseline and Mainline Security Extensions are still enabled.

Only extensions for already supported instructions are implemented in
this patch. Other extensions (MVE integer and float) will be added in
separate patches. The following configurations are allowed for Armv8.1-M
Mainline with regards to FPU and implemented in this patch:
+ no FPU (+nofp)
+ single precision VFPv5 with FP16 (+fp)
+ double precision VFPv5 with FP16 (+fp.dp)

ChangeLog entry are as follow:

*** gcc/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme <thomas.preudhomme@arm.com>

	* config/arm/arm-cpus.in (armv8_1m_main): New feature.
	(ARMv4, ARMv4t, ARMv5t, ARMv5te, ARMv5tej, ARMv6, ARMv6j, ARMv6k,
	ARMv6z, ARMv6kz, ARMv6zk, ARMv6t2, ARMv6m, ARMv7, ARMv7a, ARMv7ve,
	ARMv7r, ARMv7m, ARMv7em, ARMv8a, ARMv8_1a, ARMv8_2a, ARMv8_3a,
	ARMv8_4a, ARMv8_5a, ARMv8m_base, ARMv8m_main, ARMv8r): Reindent.
	(ARMv8_1m_main): New feature group.
	(armv8.1-m.main): New architecture.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm.c (arm_arch8_1m_main): Define and default initialize.
	(arm_option_reconfigure_globals): Initialize arm_arch8_1m_main.
	(arm_options_perform_arch_sanity_checks): Error out when targeting
	Armv8.1-M Mainline Security Extensions.
	* config/arm/arm.h (arm_arch8_1m_main): Declare.

*** gcc/testsuite/ChangeLog ***

2020-01-16  Mihail-Calin Ionescu <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme <thomas.preudhomme@arm.com>

	* lib/target-supports.exp
	(check_effective_target_arm_arch_v8_1m_main_ok): Define.
	(add_options_for_arm_arch_v8_1m_main): Likewise.
	(check_effective_target_arm_arch_v8_1m_main_multilib): Likewise.

This patch is part of a patch series to add support for Armv8.1-M
Mainline Security Extensions architecture.

Code to detect whether cmse.c can be buit with -mcmse checks the output
of host GCC when invoked with -mcmse. However, an error from the
compiler does not prevent some minimal output so this always holds true.

2020-01-16  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
2020-01-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/t-arm: Check return value of gcc rather than lack of
	output.

2020-01-16  Stam Markianos-Wright  <stam.markianos-wright@arm.com>

	* config/aarch64/aarch64-simd-builtins.def (aarch64_bfdot,
	aarch64_bfdot_lane, aarch64_bfdot_laneq): New.
	* config/aarch64/aarch64-simd.md (aarch64_bfdot, aarch64_bfdot_lane,
	aarch64_bfdot_laneq): New.
	* config/aarch64/arm_bf16.h (vbfdot_f32, vbfdotq_f32,
	vbfdot_lane_f32, vbfdotq_lane_f32, vbfdot_laneq_f32,
	vbfdotq_laneq_f32): New.
	* config/aarch64/iterators.md (UNSPEC_BFDOT, Vbfdottype,
	VBFMLA_W, VBF): New.
	(isquadop): Add V4BF, V8BF.

2020-01-16  Stam Markianos-Wright  <stam.markianos-wright@arm.com>

	* gcc.target/aarch64/advsimd-intrinsics/bfdot-1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/bfdot-2.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/bfdot-3.c: New.

Avoid comparing elements with operator== multiple times by replacing
uses of find and equal_range with equivalent inlined code that uses
operator== instead of the container's equality comparison predicate.
This is valid because the standard requires that operator== is a
refinement of the equality predicate.

Also replace the _S_is_permutation function with std::is_permutation,
which wasn't yet implemented when this code was first written.

	PR libstdc++/91263
	* include/bits/hashtable.h (_Hashtable<>): Make _Equality<> friend.
	* include/bits/hashtable_policy.h: Include <bits/stl_algo.h>.
	(_Equality_base): Remove.
	(_Equality<>::_M_equal): Review implementation. Use
	std::is_permutation.
	* testsuite/23_containers/unordered_multiset/operators/1.cc
	(Hash, Equal, test02, test03): New.
	* testsuite/23_containers/unordered_set/operators/1.cc
	(Hash, Equal, test02, test03): New.

[GCC][PATCH][AArch64]Add ACLE intrinsics for dot product (usdot - vector, <us/su>dot - by element) for AArch64 AdvSIMD ARMv8.6 Extension

gcc/ChangeLog:

2020-01-16  Stam Markianos-Wright  <stam.markianos-wright@arm.com>

	* config/aarch64/aarch64-builtins.c: (enum aarch64_type_qualifiers):
	New qualifier_lane_quadtup_index, TYPES_TERNOP_SSUS,
	TYPES_QUADOPSSUS_LANE_QUADTUP, TYPES_QUADOPSSSU_LANE_QUADTUP.
	(aarch64_simd_expand_args): Add case SIMD_ARG_LANE_QUADTUP_INDEX.
	(aarch64_simd_expand_builtin): Add qualifier_lane_quadtup_index.
	* config/aarch64/aarch64-simd-builtins.def (usdot, usdot_lane,
	usdot_laneq, sudot_lane,sudot_laneq): New.
	* config/aarch64/aarch64-simd.md (aarch64_usdot): New.
	(aarch64_<sur>dot_lane): New.
	* config/aarch64/arm_neon.h (vusdot_s32): New.
	(vusdotq_s32): New.
	(vusdot_lane_s32): New.
	(vsudot_lane_s32): New.
	* config/aarch64/iterators.md (DOTPROD_I8MM): New iterator.
	(UNSPEC_USDOT, UNSPEC_SUDOT): New unspecs.

gcc/testsuite/ChangeLog:

2020-01-16  Stam Markianos-Wright  <stam.markianos-wright@arm.com>

	* gcc.target/aarch64/advsimd-intrinsics/vdot-compile-3-1.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vdot-compile-3-2.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vdot-compile-3-3.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vdot-compile-3-4.c: New test.

As discussed on IRC, this adds a couple more checks in the
customization setup for git.  If the variables user.name and
user.email are not set anywhere in the git config hierarchy, we set
some local values.  We always ask about the values we detect and if
the user gives an answer that is new, we save that in the local
config: this gives the opportunity to use different values to those
configured for the global space.

Also cleaned up a couple of minor niggles, such as using $(cmd) rather
than `cmd` for subshells and some quoting issues when using eval.

	* gcc-git-customization.sh: Check that user.name and user.email
	are set.  Use $(cmd) instead of `cmd`.  Fix variable quoting when
	using eval.

	* value-prof.c (dump_histogram_value): Fix
	obvious spacing issue.

Hi,
  While working on bit-field lowering pass, I came across this bug.
The IR looks like:
  VIEW_CONVERT_EXPR<unsigned long>(var1) = _12;
  _1 = BIT_FIELD_REF <var1, 64, 0>;

Where the BIT_FIELD_REF has REF_REVERSE_STORAGE_ORDER set on it
and var1's type has TYPE_REVERSE_STORAGE_ORDER set on it.
PRE/FRE would decided to prop _12 into the BFR statement
which would produce wrong code.
And yes _12 has the correct byte order already; bit-field lowering
removes the implicit byte swaps in the IR and adds the explicity
to make it easier optimize later on.

This patch adds a check for storage_order_barrier_p on the lhs tree
which returns true in the case where we had a reverse order with a VCE.

ChangeLog:
* tree-ssa-sccvn.c(vn_reference_lookup_3): Check lhs for
!storage_order_barrier_p.

In struct _dep, there is an implicit padding of 4bits.  This
bit-field padding is uninitialized when init_dep_1 is being called.
This means we access uninitialized memory but never use it for
anything.  Adding an unused bit-field field and initializing it
in init_dep_1 will improve code generation also as we initialize
the whole 32bits now rather than just part of it.

ChangeLog:
* sched-int.h (_dep): Add unused bit-field field for the padding.
* sched-deps.c (init_dep_1): Init unused field.

Commit g:f96bf49a added the target field to expand_operand.
But it leaves it uninitialized when doing a full initialization
inside create_expand_operand.  This fixes the problem and improves
the code generation inside create_expand_operand too.

ChangeLog:
* optabs.h (create_expand_operand): Initialize target field also.

contrib: Verify the id to be printed is ancestor of the corresponding remote release branch (or master), otherwise print nothing.

The monotonically increasing revision ids need to be globally unique, so they should
only identify commits that were committed to the upstream repo to its master or
releases/gcc-N branches.  The alias could print something even for private branches
or vendor branches etc., but if such an identifier is then used publicly, it will
refer to something else.

2020-01-16  Jakub Jelinek  <jakub@redhat.com>

	* gcc-git-customization.sh: Verify the id to be printed is ancestor of
	the corresponding remote release branch (or master), otherwise print
	nothing.

This patch addresses the problem reported in PR92429.  When creating an
epilogue for vectorization we have to replace the SSA_NAMEs in the
PATTERN_DEF_SEQs and RELATED_STMTs of the epilogue's loop_vec_infos. When doing
this we were using simplify_replace_tree which always folds the replacement.
This may lead to a different tree-node than the one which was analyzed in
vect_loop_analyze.  In turn the new tree-node may require a different
vectorization than the one we had prepared for which caused the ICE in
question.

gcc/ChangeLog:
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR tree-optimization/92429
	* tree-ssa-loop-niter.h (simplify_replace_tree): Add parameter.
	* tree-ssa-loop-niter.c (simplify_replace_tree): Add parameter to
	control folding.
	* tree-vect-loop.c (update_epilogue_vinfo): Do not fold when replacing
	tree.

gcc/testsuite/ChangeLog:
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR tree-optimization/92429
	* gcc.dg/vect/pr92429.c: New test.

This suppresses an array out of bounds warning in mkdeps.c as proposed
by Martin Sebor in the bugzilla.

array subscript 2 is outside array bounds of ‘const char [2]’

Since this warning does occur during bootstrap it currently breaks
werror builds on IBM Z.

The problem can be reproduced also on x86_64 by changing the inlining
threshold using: --param max-inline-insns-auto=80

Bootstrapped and regression tested on x86_64 and IBM Z.

libcpp/ChangeLog:

2020-01-16  Andreas Krebbel  <krebbel@linux.ibm.com>

	PR tree-optimization/92176
	* mkdeps.c (deps_add_default_target): Avoid calling apply_vpath to
	suppress an array out of bounds warning.

The patterns used by aarch64_split_sve_subreg_move only support
integer modes, so if the widest mode is a float, we should get
its integer equivalent.

Fixes gcc.target/aarch64/sel_3.c for big-endian targets.

2020-01-16  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64.c (aarch64_split_sve_subreg_move): Apply
	aarch64_sve_int_mode to each mode.

        PR fortran/93253
        * check.c (gfc_invalid_boz): Mention -fallow-invalid-boz
        in the error message.
        * gfortran.texi (BOZ literal constants): List another missing
        extension and refer to -fallow-invalid-boz.
        * lang.opt (fallow-invalid-boz): Also mention 'X' in the help text
        as it is not covered by the previous wording.
        * primary.c (match_boz_constant): Tweak wording such that it is
        clear how to fix the nonstandard use.

        PR fortran/93253
        * fortran.dg/boz_7.f90: Updated dg-error.

gcc/ChangeLog:
	* doc/analyzer.texi (Overview): Add note about
	-fdump-ipa-analyzer.

I rewrote class impl_region_model_context to avoid using multiple
inheritance during patch review but forgot to update this comment.

Fix it.

gcc/analyzer/ChangeLog:
	* engine.cc (class impl_region_model_context): Fix comment.

This is a rather serious regression, filed in July 2019. Luckily the
fix is simple: is localized to parser.c and cp-tree.h in cp and boils
down to only a few lines.

Testing OK on x86_64-linux. Approved off-line by Jason Merrill.

	/cp
	PR c++/91073
	* cp-tree.h (is_constrained_auto): New.
	* parser.c (cp_parser_maybe_commit_to_declaration): Correctly
	handle concept-check expressions; take a cp_decl_specifier_seq*
	instead of a bool.
	(cp_parser_condition): Update call.
	(cp_parser_simple_declaration): Likewise.
	(cp_parser_placeholder_type_specifier): Correctly handle
	concept-check expressions.

	/testsuite
	PR c++/91073
	* g++.dg/concepts/pr91073-1.C: New.
	* g++.dg/concepts/pr91073-2.C: Likewise.

This change was blocking the coroutines merge, so I'm backing it out for now
to adjust my approach.

This reverts commit 7c82dd6c.

A prvalue can have void type, and if it doesn't do anything prohibited in a
constant expression, it's vacuously constant.

	* constexpr.c (verify_constant): Allow void_node.

I steered Jakub wrong on the desired behavior for temp-extend1.C in the
context of bug 92831; it doesn't make sense to try to extend the lifetime of
a temporary that we've already materialized to evaluate the test.  So this
patch munges the stabilized expression so that it won't be subject to
lifetime extension.

	* call.c (prevent_lifetime_extension): New.
	(build_conditional_expr_1): Use it.

Further improve the ctz recognition: Avoid ICEing on negative shift
counts or multiply constants.  Check the type is a char type for the
string constant case to avoid accidentally matching a wide STRING_CST.
Add a tree_expr_nonzero_p check to allow the optimization even if
CTZ_DEFINED_VALUE_AT_ZERO returns 0 or 1.  Add extra test cases.

Bootstrap OK on AArch64 and x64.

    gcc/
	PR tree-optimization/93231
	* tree-ssa-forwprop.c (optimize_count_trailing_zeroes): Check
	input_type is unsigned.  Use tree_to_shwi for shift constant.
	Check CST_STRING element size is CHAR_TYPE_SIZE bits.
	(simplify_count_trailing_zeroes): Add test to handle known non-zero
	inputs more efficiently.

    testsuite/
	PR tree-optimization/93231
	* gcc.dg/pr90838.c: New test.
	* gcc.dg/pr93231.c: New test.
	* gcc.target/aarch64/pr90838.c: Use #define u 0.

The __iota_diff_t alias can be the type __int128, but that does not
satisfy the signed_integral and __is_signed_integer_like concepts when
__STRICT_ANSI__ is defined (which is true for -std=c++2a).

Because weakly_incrementable is defined in terms of signed_integral, it
is not satisfied by __int128, which means iota_view's iterator doesn't
always satisfy input_or_output_iterator and so iota_view is not always a
range.

The solution is to define __max_size_type and __max_diff_type using
__int128, so that __is_signed_integer_like allows __int128, and then
make weakly_incrementable use __is_signed_integer_like instead of
signed_integral.

	PR libstdc++/93267
	* include/bits/iterator_concepts.h (__max_diff_type, __max_size_type):
	Move here from <bits/range_access.h> and define using __int128 when
	available.
	(__is_integer_like, __is_signed_integer_like): Move here from
	<bits/range_access.h>.
	(weakly_incrementable): Use __is_signed_integer_like.
	* include/bits/range_access.h (__max_diff_type, __max_size_type)
	(__is_integer_like, __is_signed_integer_like): Move to
	<bits/iterator_concepts.h>.
	(__make_unsigned_like_t): Move here from <ranges>.
	* include/std/ranges (__make_unsigned_like_t): Move to
	<bits/range_access.h>.
	(iota_view): Replace using-directive with using-declarations.
	* testsuite/std/ranges/iota/93267.cc: New test.
	* testsuite/std/ranges/iota_view.cc: Move to new 'iota' sub-directory.

	* config/i386/i386.md (*movsf_internal): Do not require
	SSE2 ISA for alternatives 14 and 15.