PR c++/85782

	gcc/cp/
	* cp-gimplify.c (cp_genericize_r): Call genericize_omp_for_stmt for
	OACC_LOOPs.

	gcc/testsuite/
	* c-c++-common/goacc/pr85782.c: New test.

	libgomp/
	* testsuite/libgomp.oacc-c-c++-common/pr85782.c: New test.

From-SVN: r260369

*** gcc/testsuite/ChangeLog ***

2018-05-18  Sudakshina Das  <sudi.das@arm.com>

	* gcc.target/aarch64/sve/slp_5.c: Remove xfail for tld1d and tld2d.

From-SVN: r260365

We deprecated architecture versions earlier than Armv4T in GCC 6 [1].
This patch removes support for architectures lower than Armv4.
That is the -march values armv2, armv2a, armv3, armv3m are removed
with this patch.  I did not remove armv4 because it's a bit more
involved code-wise and there has been some pushback on the implications
for -mcpu=strongarm support.

Removing armv3m and earlier though is pretty straightforward.
This allows us to get rid of the armv3m and mode32 feature bits
in arm-cpus.in as they can be assumed to be universally available.

Consequently the mcpu values arm2, arm250, arm3, arm6, arm60, arm600, arm610, arm620, arm7, arm7d, arm7di, arm70, arm700, arm700i, arm710, arm720, arm710c, arm7100, arm7500, arm7500fe, arm7m, arm7dm, arm7dm are now also removed.

Bootstrapped and tested on arm-none-linux-gnueabihf and on arm-none-eabi
with an aprofile multilib configuration (which builds quite a lot of library
configurations).

[1] https://gcc.gnu.org/gcc-6/changes.html#arm 

	* config/arm/arm-cpus.in (armv3m, mode32): Delete features.
	(ARMv4): Update.
	(ARMv2, ARMv3, ARMv3m): Delete fgroups.
	(ARMv6m): Update.
	(armv2, armv2a, armv3, armv3m): Delete architectures.
	(arm2, arm250, arm3, arm6, arm60, arm600, arm610, arm620,
	arm7, arm7d, arm7di, arm70, arm700, arm700i, arm710, arm720,
	arm710c, arm7100, arm7500, arm7500fe, arm7m, arm7dm, arm7dmi):
	Delete cpus.
	* config/arm/arm.md (maddsidi4): Remove check for arm_arch3m.
	(*mulsidi3adddi): Likewise.
	(mulsidi3): Likewise.
	(*mulsidi3_nov6): Likewise.
	(umulsidi3): Likewise.
	(umulsidi3_nov6): Likewise.
	(umaddsidi4): Likewise.
	(*umulsidi3adddi): Likewise.
	(smulsi3_highpart): Likewise.
	(*smulsi3_highpart_nov6): Likewise.
	(umulsi3_highpart): Likewise.
	(*umulsi3_highpart_nov6): Likewise.
	* config/arm/arm.h (arm_arch3m): Delete.
	* config/arm/arm.c (arm_arch3m): Delete.
	(arm_option_override_internal): Update armv3-related comment.
	(arm_configure_build_target): Delete use of isa_bit_mode32.
	(arm_option_reconfigure_globals): Delete set of arm_ach3m.
	(arm_rtx_costs_internal): Delete check of arm_arch3m.
	* config/arm/arm-fixed.md (mulsq3): Delete check for arm_arch3m.
	(mulsa3): Likewise.
	(mulusa3): Likewise.
	* config/arm/arm-protos.h (arm_arch3m): Delete.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm-tune.md: Likewise.
	* config/arm/t-arm-elf (all_early_nofp): Delete mentions of
	deleted architectures.

	* gcc.target/arm/pr62554.c: Delete.
	* gcc.target/arm/pr69610-1.c: Likewise.
	* gcc.target/arm/pr69610-2.c: Likewise.

From-SVN: r260363

The -march=armv5 and armv5e options have been deprecated in GCC 7 [1].
This patch removes support for them.
It's mostly mechanical stuff. The functionality that was previously
gated on arm_arch5 is now gated on arm_arch5t and the functionality
that was gated on arm_arch5e is now gated on arm_arch5te.

A path in TARGET_OS_CPP_BUILTINS for VxWorks is now unreachable and
therefore is deleted.

References to armv5 and armv5e are deleted/updated throughout the
source tree and testsuite.

Bootstrapped and tested on arm-none-linux-gnueabihf.
Also built a cc1 for arm-wrs-vxworks as a sanity check.

        * config/arm/arm-cpus.in (armv5, armv5e): Delete features.
        (armv5t, armv5te): New features.
        (ARMv5, ARMv5e): Delete fgroups.
        (ARMv5t, ARMv5te): Adjust for above changes.
        (ARMv6m): Likewise.
        (armv5, armv5e): Delete arches.
        * config/arm/arm.md (*call_reg_armv5): Use arm_arch5t instead of
        arm_arch5.
        (*call_reg_arm): Likewise.
        (*call_value_reg_armv5): Likewise.
        (*call_value_reg_arm): Likewise.
        (*call_symbol): Likewise.
        (*call_value_symbol): Likewise.
        (*sibcall_insn): Likewise.
        (*sibcall_value_insn): Likewise.
        (clzsi2): Likewise.
        (prefetch): Likewise.
        (define_split and define_peephole2 dependent on arm_arch5):
        Likewise.
        * config/arm/arm.h (TARGET_LDRD): Use arm_arch5te instead of
        arm_arch5e.
        (TARGET_ARM_QBIT): Likewise.
        (TARGET_DSP_MULTIPLY): Likewise.
        (enum base_architecture): Delete BASE_ARCH_5, BASE_ARCH_5E.
        (arm_arch5, arm_arch5e): Delete.
        (arm_arch5t, arm_arch5te): Declare.
        * config/arm/arm.c (arm_arch5, arm_arch5e): Delete.
        (arm_arch5t): Declare.
        (arm_option_reconfigure_globals): Update for the above.
        (arm_options_perform_arch_sanity_checks): Update comment, replace
        use of arm_arch5 with arm_arch5t.
        (use_return_insn): Likewise.
        (arm_emit_call_insn): Likewise.
        (output_return_instruction): Likewise.
        (arm_final_prescan_insn): Likewise.
        (arm_coproc_builtin_available): Likewise.
        * config/arm/arm-c.c (arm_cpu_builtins): Replace arm_arch5 and
        arm_arch5e with arm_arch5t and arm_arch5te.
        * config/arm/arm-protos.h (arm_arch5, arm_arch5e): Delete.
        (arm_arch5t, arm_arch5te): Declare.
        * config/arm/arm-tables.opt: Regenerate.
        * config/arm/t-arm-elf: Remove references to armv5, armv5e.
        * config/arm/t-multilib: Likewise.
        * config/arm/thumb1.md (*call_reg_thumb1_v5): Check arm_arch5t
        instead of arm_arch5.
        (*call_reg_thumb1): Likewise.
        (*call_value_reg_thumb1_v5): Likewise.
        (*call_value_reg_thumb1): Likewise.
        * config/arm/vxworks.h (TARGET_OS_CPP_BUILTINS): Remove now
        unreachable path.
        * doc/invoke.texi (ARM Options): Remove references to armv5, armv5e.

        * gcc.target/arm/pr40887.c: Update comment.
        * lib/target-supports.exp: Don't generate effective target checks
        and related helpers for armv5.  Update comment.
        * gcc.target/arm/armv5_thumb_isa.c: Delete.
        * gcc.target/arm/di-longlong64-sync-withhelpers.c: Update effective
        target check and options.

        * config/arm/libunwind.S: Update comment relating to armv5.

From-SVN: r260362

2018-05-18  Martin Liska  <mliska@suse.cz>

	PR gcov-profile/84846
	* gcov.c (print_usage): Add new -t option.
	(process_args): Handle the option.
	(generate_results): Use stdout as output when requested by
	the option.
2018-05-18  Martin Liska  <mliska@suse.cz>

	PR gcov-profile/84846
	* doc/gcov.texi: Document -t option of gcov tool.

From-SVN: r260361

2018-05-18  Martin Liska  <mliska@suse.cz>

	PR gcov-profile/84846
	* coverage.c (coverage_init): Write PWD to .gcno file.
	* doc/gcov.texi: Document how working directory is printed.
	* gcov-dump.c (dump_gcov_file): Print PWD.
	* gcov.c (output_intermediate_file): Likewise.
	(read_graph_file): Read PWD string.
	(output_lines): Print PWD.

From-SVN: r260359

2018-05-18  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>

	PR middle-end/85817
	* ipa-pure-const.c (malloc_candidate_p): Remove the check integer_zerop
	for retval and return false if all args to phi are zero.	

testsuite/
	* gcc.dg/tree-ssa/pr83648.c: Change scan-tree-dump to
	scan-tree-dump-not for h.

From-SVN: r260358

2018-05-18  Richard Biener  <rguenther@suse.de>

	* gimple-ssa-evrp.c (class evrp_folder): Add simplify_stmt_using_ranges
	method.
	(evrp_dom_walker::before_dom_children): Call it.

	* gcc.dg/tree-ssa/pr21559.c: Adjust.
	* gcc.dg/tree-ssa/pr45397.c: Likewise.
	* gcc.dg/tree-ssa/pr61839_1.c: Likewise.
	* gcc.dg/tree-ssa/pr61839_2.c: Likewise.
	* gcc.dg/tree-ssa/pr61839_4.c: Likewise.
	* gcc.dg/tree-ssa/vrp17.c: Likewise.
	* gcc.dg/tree-ssa/vrp18.c: Likewise.
	* gcc.dg/tree-ssa/vrp23.c: Likewise.
	* gcc.dg/tree-ssa/vrp24.c: Likewise.
	* gcc.dg/tree-ssa/vrp58.c: Likewise.
	* gcc.dg/vrp-min-max-1.c: Likewise.
	* gcc.dg/vrp-min-max-3.c: New testcase.

From-SVN: r260357

tree-dfa.c (get_ref_base_and_extent): Use range-info to refine results when processing array refs with variable index.

2018-05-18  Richard Biener  <rguenther@suse.de>

	* tree-dfa.c (get_ref_base_and_extent): Use range-info to refine
	results when processing array refs with variable index.

	* gcc.dg/tree-ssa/ssa-dse-35.c: New testcase.
	* gcc.dg/graphite/scop-10.c: Adjust to avoid dead code.
	* gcc.dg/graphite/scop-6.c: Likewise.
	* gcc.dg/graphite/scop-7.c: Likewise.
	* gcc.dg/graphite/scop-8.c: Likewise.
	* gcc.dg/graphite/scop-9.c: Likewise.

From-SVN: r260354

2018-05-18  Toon Moene  <toon@moene.org>

	* doc/invoke.texi: Move -floop-unroll-and-jam documentation
	directly after that of -floop-interchange. Indicate that both
	options are enabled by default when specifying -O3.

From-SVN: r260352

We've a deficiency in our vec_set family of patterns.
We don't support directly loading a vector lane using LD1 for V2DImode and all the vector floating-point modes.
We do do it correctly for the other integer vector modes (V4SI, V8HI etc) though.

The alternatives on the relative floating-point patterns only allow a register-to-register INS instruction.
That means if we want to load a value into a vector lane we must first load it into a scalar register and then
perform an INS, which is wasteful.

There is also an explicit V2DI vec_set expander dangling around for no reason that I can see. It seems to do the
exact same things as the other vec_set expanders. This patch removes that.
It now unifies all vec_set expansions into a single "vec_set<mode>" define_expand using the catch-all VALL_F16 iterator. 

With this patch we avoid loading values into scalar registers and then doing an explicit INS on them to move them into
the desired vector lanes. For example for:

typedef float v4sf __attribute__ ((vector_size (16)));
typedef long long v2di __attribute__ ((vector_size (16)));

v2di
foo_v2di (long long *a, long long *b)
{
  v2di res = { *a, *b };
  return res;
}

v4sf
foo_v4sf (float *a, float *b, float *c, float *d)
{
  v4sf res = { *a, *b, *c, *d };
  return res;
}

we currently generate:

foo_v2di:
        ldr     d0, [x0]
        ldr     x0, [x1]
        ins     v0.d[1], x0
        ret

foo_v4sf:
        ldr     s0, [x0]
        ldr     s3, [x1]
        ldr     s2, [x2]
        ldr     s1, [x3]
        ins     v0.s[1], v3.s[0]
        ins     v0.s[2], v2.s[0]
        ins     v0.s[3], v1.s[0]
        ret

but with this patch we generate the much cleaner:
foo_v2di:
        ldr     d0, [x0]
        ld1     {v0.d}[1], [x1]
        ret

foo_v4sf:
        ldr     s0, [x0]
        ld1     {v0.s}[1], [x1]
        ld1     {v0.s}[2], [x2]
        ld1     {v0.s}[3], [x3]
        ret


	* config/aarch64/aarch64-simd.md (vec_set<mode>): Use VALL_F16 mode
	iterator.  Delete separate integer-mode vec_set<mode> expander.
	(aarch64_simd_vec_setv2di): Delete.
	(vec_setv2di): Delete.
	(aarch64_simd_vec_set<mode>): Delete all other patterns with that name.
	Use VALL_F16 mode iterator.  Add LD1 alternative and use vwcore for
	the "w, r" alternative.

	* gcc.target/aarch64/vect-init-ld1.c: New test.

From-SVN: r260351

2018-05-18  Martin Liska  <mliska@suse.cz>

	* passes.def: Add pass_lower_switch and pass_lower_switch_O0.
	* tree-pass.h (make_pass_lower_switch_O0): New function.
	* tree-switch-conversion.c (node_has_low_bound): Remove.
	(node_has_high_bound): Likewise.
	(node_is_bounded): Likewise.
	(class pass_lower_switch): Make it a template type and create
	two instances.
	(pass_lower_switch::execute): Add template argument.
	(make_pass_lower_switch): New function.
	(make_pass_lower_switch_O0): New function.
	(do_jump_if_equal): Remove.
	(emit_case_nodes): Simplify to just handle all 3 cases and leave
	all the hard work to tree optimization passes.
2018-05-18  Martin Liska  <mliska@suse.cz>

	* gcc.dg/tree-ssa/vrp104.c: Adjust dump file that is scanned.
	* gcc.dg/tree-prof/update-loopch.c: Likewise.

From-SVN: r260350

2018-05-18  Martin Liska  <mliska@suse.cz>

	* dbgcnt.c (limit_low): Renamed from limit.
	(limit_high): New variable.
	(dbg_cnt_is_enabled): Check for upper limit.
	(dbg_cnt): Adjust dumping.
	(dbg_cnt_set_limit_by_index): Add new argument for high
	value.
	(dbg_cnt_set_limit_by_name): Likewise.
	(dbg_cnt_process_single_pair): Parse new format.
	(dbg_cnt_process_opt): Use strtok.
	(dbg_cnt_list_all_counters): Remove 'value' and add
	'limit_high'.
	* doc/invoke.texi: Document changes.
2018-05-18  Martin Liska  <mliska@suse.cz>

	* gcc.dg/ipa/ipa-icf-39.c: New test.
	* gcc.dg/pr68766.c: Adjust pruned output.

From-SVN: r260349

There are four optabs for various forms of fused multiply-add:
fma, fms, fnma and fnms.  Of these, only fma had a direct gimple
representation.  For the other three we relied on special pattern-
matching during expand, although tree-ssa-math-opts.c did have
some code to try to second-guess what expand would do.

This patch removes the old FMA_EXPR representation of fma and
introduces four new internal functions, one for each optab.
IFN_FMA is tied to BUILT_IN_FMA* while the other three are
independent directly-mapped internal functions.  It's then
possible to do the pattern-matching in match.pd and
tree-ssa-math-opts.c (via folding) can select the exact
FMA-based operation.

The BRIG & HSA parts are a best guess, but seem relatively simple.

2018-05-18  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	* doc/sourcebuild.texi (scalar_all_fma): Document.
	* tree.def (FMA_EXPR): Delete.
	* internal-fn.def (FMA, FMS, FNMA, FNMS): New internal functions.
	* internal-fn.c (ternary_direct): New macro.
	(expand_ternary_optab_fn): Likewise.
	(direct_ternary_optab_supported_p): Likewise.
	* Makefile.in (build/genmatch.o): Depend on case-fn-macros.h.
	* builtins.c (fold_builtin_fma): Delete.
	(fold_builtin_3): Don't call it.
	* cfgexpand.c (expand_debug_expr): Remove FMA_EXPR handling.
	* expr.c (expand_expr_real_2): Likewise.
	* fold-const.c (operand_equal_p): Likewise.
	(fold_ternary_loc): Likewise.
	* gimple-pretty-print.c (dump_ternary_rhs): Likewise.
	* gimple.c (DEFTREECODE): Likewise.
	* gimplify.c (gimplify_expr): Likewise.
	* optabs-tree.c (optab_for_tree_code): Likewise.
	* tree-cfg.c (verify_gimple_assign_ternary): Likewise.
	* tree-eh.c (operation_could_trap_p): Likewise.
	(stmt_could_throw_1_p): Likewise.
	* tree-inline.c (estimate_operator_cost): Likewise.
	* tree-pretty-print.c (dump_generic_node): Likewise.
	(op_code_prio): Likewise.
	* tree-ssa-loop-im.c (stmt_cost): Likewise.
	* tree-ssa-operands.c (get_expr_operands): Likewise.
	* tree.c (commutative_ternary_tree_code, add_expr): Likewise.
	* fold-const-call.h (fold_fma): Delete.
	* fold-const-call.c (fold_const_call_ssss): Handle CFN_FMS,
	CFN_FNMA and CFN_FNMS.
	(fold_fma): Delete.
	* genmatch.c (combined_fn): New enum.
	(commutative_ternary_tree_code): Remove FMA_EXPR handling.
	(commutative_op): New function.
	(commutate): Use it.  Handle more than 2 operands.
	(dt_operand::gen_gimple_expr): Use commutative_op.
	(parser::parse_expr): Allow :c to be used with non-binary
	operators if the commutative operand is known.
	* gimple-ssa-backprop.c (backprop::process_builtin_call_use): Handle
	CFN_FMS, CFN_FNMA and CFN_FNMS.
	(backprop::process_assign_use): Remove FMA_EXPR handling.
	* hsa-gen.c (gen_hsa_insns_for_operation_assignment): Likewise.
	(gen_hsa_fma): New function.
	(gen_hsa_insn_for_internal_fn_call): Use it for IFN_FMA, IFN_FMS,
	IFN_FNMA and IFN_FNMS.
	* match.pd: Add folds for IFN_FMS, IFN_FNMA and IFN_FNMS.
	* gimple-fold.h (follow_all_ssa_edges): Declare.
	* gimple-fold.c (follow_all_ssa_edges): New function.
	* tree-ssa-math-opts.c (convert_mult_to_fma_1): Use the
	gimple_build interface and use follow_all_ssa_edges to fold the result.
	(convert_mult_to_fma): Use direct_internal_fn_suppoerted_p
	instead of checking for optabs directly.
	* config/i386/i386.c (ix86_add_stmt_cost): Recognize FMAs as calls
	rather than FMA_EXPRs.
	* config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Create a
	call to IFN_FMA instead of an FMA_EXPR.

gcc/brig/
	* brigfrontend/brig-function.cc
	(brig_function::get_builtin_for_hsa_opcode): Use BUILT_IN_FMA
	for BRIG_OPCODE_FMA.
	(brig_function::get_tree_code_for_hsa_opcode): Treat BUILT_IN_FMA
	as a call.

gcc/c/
	* gimple-parser.c (c_parser_gimple_postfix_expression): Remove
	__FMA_EXPR handlng.

gcc/cp/
	* constexpr.c (cxx_eval_constant_expression): Remove FMA_EXPR handling.
	(potential_constant_expression_1): Likewise.

gcc/testsuite/
	* lib/target-supports.exp (check_effective_target_scalar_all_fma):
	New proc.
	* gcc.dg/fma-1.c: New test.
	* gcc.dg/fma-2.c: Likewise.
	* gcc.dg/fma-3.c: Likewise.
	* gcc.dg/fma-4.c: Likewise.
	* gcc.dg/fma-5.c: Likewise.
	* gcc.dg/fma-6.c: Likewise.
	* gcc.dg/fma-7.c: Likewise.
	* gcc.dg/gimplefe-26.c: Use .FMA instead of __FMA and require
	scalar_all_fma.
	* gfortran.dg/reassoc_7.f: Pass -ffp-contract=off.
	* gfortran.dg/reassoc_8.f: Likewise.
	* gfortran.dg/reassoc_9.f: Likewise.
	* gfortran.dg/reassoc_10.f: Likewise.

From-SVN: r260348

From-SVN: r260347

	* line-map.c (linemap_init): Use placement new.

	* system.h: #include <new>.

From-SVN: r260343

	gcc/
	* expr.c (do_tablejump): When converting index to Pmode, if we have a
	sign extended promoted subreg, and the range does not have the sign bit
	set, then do a sign extend.

	* config/riscv/riscv.c (riscv_extend_comparands): In unsigned QImode
	test, check for sign extended subreg and/or constant operands, and
	do a sign extend in that case.

	gcc/testsuite/
	* gcc.target/riscv/switch-qi.c: New.
	* gcc.target/riscv/switch-si.c: New.

From-SVN: r260340

2018-05-17  Steve Ellcey  <sellcey@cavium.com>

	* config/aarch64/thunderx2t99.md (thunderx2t99_ls_both): Delete.
	(thunderx2t99_multiple): Delete psuedo-units from used cpus.
	Add untyped.
	(thunderx2t99_alu_shift): Remove alu_shift_reg, alus_shift_reg.
	Change logics_shift_reg to logics_shift_imm.
	(thunderx2t99_fp_loadpair_basic): Delete.
	(thunderx2t99_fp_storepair_basic): Delete.
	(thunderx2t99_asimd_int): Add neon_sub and neon_sub_q types.
	(thunderx2t99_asimd_polynomial): Delete.
	(thunderx2t99_asimd_fp_simple): Add neon_fp_mul_s_scalar_q
	and neon_fp_mul_d_scalar_q.
	(thunderx2t99_asimd_fp_conv): Add *int_to_fp* types.
	(thunderx2t99_asimd_misc): Delete neon_dup and neon_dup_q.
	(thunderx2t99_asimd_recip_step): Add missing *sqrt* types.
	(thunderx2t99_asimd_lut): Add missing tbl types.
	(thunderx2t99_asimd_ext): Delete.
	(thunderx2t99_asimd_load1_1_mult): Delete.
	(thunderx2t99_asimd_load1_2_mult): Delete.
	(thunderx2t99_asimd_load1_ldp): New.
	(thunderx2t99_asimd_load1): New.
	(thunderx2t99_asimd_load2): Add missing *load2* types.
	(thunderx2t99_asimd_load3): New.
	(thunderx2t99_asimd_load4): New.
	(thunderx2t99_asimd_store1_1_mult): Delete.
	(thunderx2t99_asimd_store1_2_mult): Delete.
	(thunderx2t99_asimd_store2_mult): Delete.
	(thunderx2t99_asimd_store2_onelane): Delete.
	(thunderx2t99_asimd_store_stp): New.
	(thunderx2t99_asimd_store1): New.
	(thunderx2t99_asimd_store2): New.
	(thunderx2t99_asimd_store3): New.
	(thunderx2t99_asimd_store4): New.

From-SVN: r260335

2018-05-17  Jerome Lambourg  <lambourg@adacore.com>

	gcc/
	* config/arm/arm_cmse.h (cmse_nsfptr_create, cmse_is_nsfptr): Remove
	#include <stdint.h>.  Replace intptr_t with __INTPTR_TYPE__.

	libgcc/
	* config/arm/cmse.c (cmse_check_address_range): Replace
	UINTPTR_MAX with __UINTPTR_MAX__ and uintptr_t with __UINTPTR_TYPE__.

From-SVN: r260330

	PR target/85698
	* config/rs6000/rs6000.c (rs6000_output_move_128bit): Check dest operand.

	* gcc.target/powerpc/pr85698.c: New test.


Co-Authored-By: Segher Boessenkool <segher@kernel.crashing.org>

From-SVN: r260329

Because path.cc is compiled with -std=gnu++17 the static constexpr
data member is implicitly 'inline' and so no definition gets emitted
unless it gets used in that translation unit. Other translation units
built as C++11 or C++14 still require a namespace-scope definition of
the variable, so mark the definition as used.

	PR libstdc++/85818
	* src/filesystem/path.cc (path::preferred_separator): Add used
	attribute.
	* testsuite/experimental/filesystem/path/preferred_separator.cc: New.

From-SVN: r260326

	PR libstdc++/85812
	* libsupc++/cxxabi_init_exception.h (__cxa_free_exception): Declare.
	* libsupc++/exception_ptr.h (make_exception_ptr) [__cpp_exceptions]:
	Refactor to separate non-throwing and throwing implementations.
	[__cpp_rtti && !_GLIBCXX_HAVE_CDTOR_CALLABI]: Deallocate the memory
	if constructing the object throws.

From-SVN: r260323

tree-ssa-dse.c (dse_classify_store): Fix iterator increment for pruning loop and prune defs feeding only already...

2018-05-17  Richard Biener  <rguenther@suse.de>

	* tree-ssa-dse.c (dse_classify_store): Fix iterator increment
	for pruning loop and prune defs feeding only already visited PHIs.

From-SVN: r260322

2018-05-17  Richard Biener  <rguenther@suse.de>

	* tree-ssa-sccvn.c (vn_reference_lookup_3): Improve memset handling.

	* gcc.dg/tree-ssa/ssa-fre-63.c: New testcase.

From-SVN: r260318

	PR tree-optimization/85793
	* tree-vect-stmts.c (vectorizable_load): Handle 1 element-wise load
	for VMAT_ELEMENTWISE.

	gcc/testsuite
	* gcc.dg/vect/pr85793.c: New test.

Co-Authored-By: Richard Biener <rguenther@suse.de>

From-SVN: r260317

This patch gets the gimple FE to parse calls to internal functions.
The only non-obvious thing was how the functions should be written
to avoid clashes with real function names.  One option would be to
go the magic number of underscores route, but we already do that for
built-in functions, and it would be good to keep them visually
distinct.  In the end I borrowed the local/internal label convention
from asm and used:

  x = .SQRT (y);

2018-05-17  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	* internal-fn.h (lookup_internal_fn): Declare
	* internal-fn.c (lookup_internal_fn): New function.
	* gimple.c (gimple_build_call_from_tree): Handle calls to
	internal functions.
	* gimple-pretty-print.c (dump_gimple_call): Print "." before
	internal function names.
	* tree-pretty-print.c (dump_generic_node): Likewise.
	* tree-ssa-scopedtables.c (expr_hash_elt::print): Likewise.

gcc/c/
	* gimple-parser.c: Include internal-fn.h.
	(c_parser_gimple_statement): Treat a leading CPP_DOT as a call.
	(c_parser_gimple_call_internal): New function.
	(c_parser_gimple_postfix_expression): Use it to handle CPP_DOT.
	Fix typos in comment.

gcc/testsuite/
	* gcc.dg/gimplefe-28.c: New test.
	* gcc.dg/asan/use-after-scope-9.c: Adjust expected output for
	internal function calls.
	* gcc.dg/goacc/loop-processing-1.c: Likewise.

From-SVN: r260316

This patch makes the function versions of gimple_build and
gimple_simplify take combined_fns rather than built_in_codes,
so that they work with internal functions too.  The old
gimple_builds were unused, so no existing callers need
to be updated.

2018-05-17  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	* gimple-fold.h (gimple_build): Make the function forms take
	combined_fn rather than built_in_function.
	(gimple_simplify): Likewise.
	* gimple-match-head.c (gimple_simplify): Likewise.
	* gimple-fold.c (gimple_build): Likewise.
	* tree-vect-loop.c (get_initial_def_for_reduction): Use gimple_build
	rather than gimple_build_call_internal.
	(get_initial_defs_for_reduction): Likewise.
	(vect_create_epilog_for_reduction): Likewise.
	(vectorizable_live_operation): Likewise.

From-SVN: r260315

2018-05-17  Martin Liska  <mliska@suse.cz>

	* gimple-ssa-sprintf.c (format_directive): Do not use
	space in between 'G_' and '('.
2018-05-17  Martin Liska  <mliska@suse.cz>

	* c-warn.c (overflow_warning): Do not use
	space in between 'G_' and '('.
2018-05-17  Martin Liska  <mliska@suse.cz>

	* gcc.dg/plugin/ggcplug.c (plugin_init): Do not use
	space in between 'G_' and '('.

From-SVN: r260314

	PR target/85323
	* config/i386/i386.c (ix86_fold_builtin): Handle masked shifts
	even if the mask is not all ones.

	* gcc.target/i386/pr85323-7.c: New test.
	* gcc.target/i386/pr85323-8.c: New test.
	* gcc.target/i386/pr85323-9.c: New test.

From-SVN: r260313

	PR target/85323
	* config/i386/i386.c (ix86_fold_builtin): Fold shift builtins by
	vector.
	(ix86_gimple_fold_builtin): Likewise.

	* gcc.target/i386/pr85323-4.c: New test.
	* gcc.target/i386/pr85323-5.c: New test.
	* gcc.target/i386/pr85323-6.c: New test.

From-SVN: r260312

	PR target/85323
	* config/i386/i386.c: Include tree-vector-builder.h.
	(ix86_vector_shift_count): New function.
	(ix86_fold_builtin): Fold shift builtins by scalar count.
	(ix86_gimple_fold_builtin): Likewise.

	* gcc.target/i386/pr85323-1.c: New test.
	* gcc.target/i386/pr85323-2.c: New test.
	* gcc.target/i386/pr85323-3.c: New test.

From-SVN: r260311

	* config/i386/avx512fintrin.h (_mm512_set_epi16, _mm512_set_epi8,
	_mm512_setzero): New intrinsics.

	* gcc.target/i386/avx512f-set-v32hi-1.c: New test.
	* gcc.target/i386/avx512f-set-v32hi-2.c: New test.
	* gcc.target/i386/avx512f-set-v32hi-3.c: New test.
	* gcc.target/i386/avx512f-set-v32hi-4.c: New test.
	* gcc.target/i386/avx512f-set-v32hi-5.c: New test.
	* gcc.target/i386/avx512f-set-v64qi-1.c: New test.
	* gcc.target/i386/avx512f-set-v64qi-2.c: New test.
	* gcc.target/i386/avx512f-set-v64qi-3.c: New test.
	* gcc.target/i386/avx512f-set-v64qi-4.c: New test.
	* gcc.target/i386/avx512f-set-v64qi-5.c: New test.
	* gcc.target/i386/avx512f-setzero-1.c: New test.

From-SVN: r260310

In the testcase in this patch we create an SLP vector with only two
elements. Our current vector initialisation code will first duplicate
the first element to both lanes, then overwrite the top lane with a new
value.

This duplication can be clunky and wasteful.

Better would be to simply use the fact that we will always be
overwriting the remaining bits, and simply move the first element to the corrcet
place (implicitly zeroing all other bits).

This reduces the code generation for this case, and can allow more
efficient addressing modes, and other second order benefits for AArch64
code which has been vectorized to V2DI mode.

Note that the change is generic enough to catch the case for any vector
mode, but is expected to be most useful for 2x64-bit vectorization.

Unfortunately, on its own, this would cause failures in
gcc.target/aarch64/load_v2vec_lanes_1.c and
gcc.target/aarch64/store_v2vec_lanes.c , which expect to see many more
vec_merge and vec_duplicate for their simplifications to apply. To fix
this,
add a special case to the AArch64 code if we are loading from two memory
addresses, and use the load_pair_lanes patterns directly.

We also need a new pattern in simplify-rtx.c:simplify_ternary_operation
to catch:

  (vec_merge:OUTER
     (vec_duplicate:OUTER x:INNER)
     (subreg:OUTER y:INNER 0)
     (const_int N))

And simplify it to:

  (vec_concat:OUTER x:INNER y:INNER) or (vec_concat y x)

This is similar to the existing patterns which are tested in this
function, without requiring the second operand to also be a vec_duplicate. 

	* config/aarch64/aarch64.c (aarch64_expand_vector_init): Modify
	code generation for cases where splatting a value is not useful.
	* simplify-rtx.c (simplify_ternary_operation): Simplify
	vec_merge across a vec_duplicate and a paradoxical subreg forming a vector
	mode to a vec_concat.

	* gcc.target/aarch64/vect-slp-dup.c: New.


Co-Authored-By: Kyrylo Tkachov <kyrylo.tkachov@arm.com>

From-SVN: r260309

2018-05-17  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/85713
	* g++.dg/cpp1y/lambda-generic-85713-2.C: New.

From-SVN: r260308

2018-05-17  Olga Makhotina  <olga.makhotina@intel.com>

gcc/

	* config.gcc: Support "goldmont-plus".
	* config/i386/driver-i386.c (host_detect_local_cpu): Detect
	"goldmont-plus".
	* config/i386/i386-c.c (ix86_target_macros_internal): Handle
	PROCESSOR_GOLDMONT_PLUS.
	* config/i386/i386.c (m_GOLDMONT_PLUS): Define.
	(processor_target_table): Add "goldmont-plus".
	(PTA_GOLDMONT_PLUS): Define.
	(ix86_lea_outperforms): Add TARGET_GOLDMONT_PLUS.
	(get_builtin_code_for_version): Handle PROCESSOR_GOLDMONT_PLUS.
	(fold_builtin_cpu): Add M_INTEL_GOLDMONT_PLUS.
	(fold_builtin_cpu): Add "goldmont-plus".
	(ix86_add_stmt_cost): Add TARGET_GOLDMONT_PLUS.
	(ix86_option_override_internal): Add "goldmont-plus".
	* config/i386/i386.h (processor_costs): Define TARGET_GOLDMONT_PLUS.
	(processor_type): Add PROCESSOR_GOLDMONT_PLUS.
	* config/i386/x86-tune.def: Add m_GOLDMONT_PLUS.
	* doc/invoke.texi: Add goldmont-plus as x86 -march=/-mtune= CPU type.

libgcc/

	* config/i386/cpuinfo.h (processor_types): Add INTEL_GOLDMONT_PLUS.
	* config/i386/cpuinfo.c (get_intel_cpu): Detect Goldmont Plus.

gcc/testsuite/

	* gcc.target/i386/builtin_target.c: Test goldmont-plus.
	* gcc.target/i386/funcspec-56.inc: Test arch=goldmont-plus.

From-SVN: r260307

2018-05-17  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/85757
	* tree-ssa-dse.c (dse_classify_store): Record a PHI def and
	remove defs that only feed that PHI from further processing.

	* gcc.dg/tree-ssa/ssa-dse-34.c: New testcase.

From-SVN: r260306

From-SVN: r260304

re PR c++/85363 (Throwing exception from member constructor (brace initializer vs initializer list))

	PR c++/85363
	* call.c (set_flags_from_callee): Handle AGGR_INIT_EXPRs too.
	* tree.c (bot_manip): Call set_flags_from_callee for
	AGGR_INIT_EXPRs too.

	* g++.dg/cpp0x/initlist-throw1.C: New test.
	* g++.dg/cpp0x/initlist-throw2.C: New test.

From-SVN: r260300

	gcc/
	* config/riscv/riscv.md (<optab>si3_mask, <optab>si3_mask_1): Prepend
	asterisk to name.
	(<optab>di3_mask, <optab>di3_mask_1): Likewise.

From-SVN: r260299

DWARF5 defines a small header for .debug_str_offsets.  Since we only use
it for split dwarf .dwo files we don't need to keep track of the actual
index offset in an attribute.

gcc/ChangeLog

	* dwarf2out.c (count_index_strings): New function.
	(output_indirect_strings): Call count_index_strings and generate
	header for dwarf_version >= 5.

From-SVN: r260298