This patch removes the LIBGCC2_HAS_{SF,DF,XF,TF}_MODE target macros,
replacing them by predefines with -fbuilding-libgcc, together with a
target hook that can influence those predefines when needed.

The new default is that a floating-point mode is supported in libgcc
if (a) it passes the scalar_mode_supported_p hook (otherwise it's not
plausible for it to be supported in libgcc) and (b) it's one of those
four modes (since those are the modes for which libgcc hardcodes the
possibility of support).  The target hook can override the default
choice (in either direction) for modes that pass
scalar_mode_supported_p (although overriding in the direction of
returning true when the default would return false only makes sense if
all relevant functions are specially defined in libgcc for that
particular target).

The previous default settings depended on various settings such as
LIBGCC2_LONG_DOUBLE_TYPE_SIZE, as well as targets defining the above
target macros if the default wasn't correct.

The default scalar_mode_supported_p only declares a floating-point
mode to be supported if it matches one of float / double / long
double.  This means that in most cases where a mode is only supported
conditionally in libgcc (TFmode only supported if it's the mode of
long double, most commonly), the default gets things right.  Overrides
were needed in the following cases:

* SFmode would always have been supported in libgcc (the condition was
  BITS_PER_UNIT == 8, true for all current targets), but pdp11
  defaults to 64-bit float, and in that case SFmode would fail
  scalar_mode_supported_p.  I don't know if libgcc actually built for
  pdp11 (and the port may well no longer be being used), but this
  patch adds a scalar_mode_supported_p hook to it to ensure SFmode is
  treated as supported.

* Certain i386 and ia64 targets need the new hook to match the
  existing cases for when XFmode or TFmode support is present in
  libgcc.  For i386, the hook can always declare XFmode to be
  supported - the cases where it's not are the cases where long double
  is TFmode, in which case XFmode fails scalar_mode_supported_p[*] -
  but TFmode support needs to be conditional.  (And of the targets not
  defining LIBGCC2_HAS_TF_MODE before this patch, some defined
  LONG_DOUBLE_TYPE_SIZE to 64, so ensuring LIBGCC2_HAS_TF_MODE would
  always be false, while others did not define it, so allowing it to
  be true in the -mlong-double-128 case.  This patch matches that
  logic, although I suspect all the latter targets would have been
  broken if you tried to enable -mlong-double-128 by default, for lack
  of the soft-fp TFmode support in libgcc, which is separately
  configured.)

  [*] I don't know if it's deliberate not to support __float80 at all
  with -mlong-double-128.

In order to implement the default version of the new hook,
insn-modes.h was made to contain macros such as HAVE_TFmode for each
machine mode, so the default hook can contain conditionals on whether
XFmode and TFmode exist (to match the hardcoding of a list of modes in
libgcc).  This is also used in fortran/trans-types.c; previously it
had a conditional on defined(LIBGCC2_HAS_TF_MODE) (a bit dubious,
since it ignored the value of the macro), which is replaced by testing
defined(HAVE_TFmode), in conjunction with requiring
targetm.libgcc_floating_mode_supported_p.

(Fortran is testing something stronger than that hook: not only is
libgcc support required, but also libm or equivalent.  Thus, it has a
test for ENABLE_LIBQUADMATH_SUPPORT in the case that the mode is
TFmode and that's not the same as any of the three standard types.
The old and new tests are intended to accept exactly the same set of
modes for all targets.)

Apart from the four target macros eliminated by this patch, it gets us
closer to eliminating LIBGCC2_LONG_DOUBLE_TYPE_SIZE as well, though a
few more places using that macro need changing first.

Bootstrapped with no regressions on x86_64-unknown-linux-gnu; also
built cc1 for crosses to ia64-elf and pdp11-none as a minimal test of
changes for those targets.

gcc:
	* target.def (libgcc_floating_mode_supported_p): New hook.
	* targhooks.c (default_libgcc_floating_mode_supported_p): New
	function.
	* targhooks.h (default_libgcc_floating_mode_supported_p): Declare.
	* doc/tm.texi.in (LIBGCC2_HAS_DF_MODE, LIBGCC2_HAS_XF_MODE)
	(LIBGCC2_HAS_TF_MODE): Remove.
	(TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P): New @hook.
	* doc/tm.texi: Regenerate.
	* genmodes.c (emit_insn_modes_h): Define HAVE_%smode for each
	machine mode.
	* system.h (LIBGCC2_HAS_SF_MODE, LIBGCC2_HAS_DF_MODE)
	(LIBGCC2_HAS_XF_MODE, LIBGCC2_HAS_TF_MODE): Poison.
	* config/i386/cygming.h (LIBGCC2_HAS_TF_MODE): Remove.
	* config/i386/darwin.h (LIBGCC2_HAS_TF_MODE): Remove.
	* config/i386/djgpp.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
	* config/i386/dragonfly.h (LIBGCC2_HAS_TF_MODE): Remove.
	* config/i386/freebsd.h (LIBGCC2_HAS_TF_MODE): Remove.
	* config/i386/gnu-user-common.h (LIBGCC2_HAS_TF_MODE): Remove.
	* config/i386/i386-interix.h (IX86_NO_LIBGCC_TFMODE): Define.
	* config/i386/i386.c (ix86_libgcc_floating_mode_supported_p): New
	function.
	(TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P): Define.
	* config/i386/i386elf.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
	* config/i386/lynx.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
	* config/i386/netbsd-elf.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
	* config/i386/netbsd64.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
	* config/i386/nto.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
	* config/i386/openbsd.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
	* config/i386/openbsdelf.h (LIBGCC2_HAS_TF_MODE): Remove.
	* config/i386/rtemself.h (IX86_NO_LIBGCC_TFMODE): Define.
	* config/i386/sol2.h (LIBGCC2_HAS_TF_MODE): Remove.
	* config/i386/vx-common.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
	* config/ia64/elf.h (IA64_NO_LIBGCC_TFMODE): Define.
	* config/ia64/freebsd.h (IA64_NO_LIBGCC_TFMODE): Define.
	* config/ia64/hpux.h (LIBGCC2_HAS_XF_MODE, LIBGCC2_HAS_TF_MODE):
	Remove.
	* config/ia64/ia64.c (TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P):
	New macro.
	(ia64_libgcc_floating_mode_supported_p): New function.
	* config/ia64/linux.h (LIBGCC2_HAS_TF_MODE): Remove.
	* config/ia64/vms.h (IA64_NO_LIBGCC_XFMODE)
	(IA64_NO_LIBGCC_TFMODE): Define.
	* config/msp430/msp430.h (LIBGCC2_HAS_DF_MODE): Remove.
	* config/pdp11/pdp11.c (TARGET_SCALAR_MODE_SUPPORTED_P): New
	macro.
	(pdp11_scalar_mode_supported_p): New function.
	* config/rl78/rl78.h (LIBGCC2_HAS_DF_MODE): Remove.
	* config/rx/rx.h (LIBGCC2_HAS_DF_MODE): Remove.

gcc/c-family:
	* c-cppbuiltin.c (c_cpp_builtins): Define __LIBGCC_HAS_%s_MODE__
	macros for floating-point modes.

gcc/fortran:
	* trans-types.c (gfc_init_kinds): Check
	targetm.libgcc_floating_mode_supported_p for floating-point
	modes.  Check HAVE_TFmode instead of LIBGCC2_HAS_TF_MODE.

libgcc:
	* libgcc2.h (LIBGCC2_HAS_SF_MODE): Define using
	__LIBGCC_HAS_SF_MODE__.
	(LIBGCC2_HAS_DF_MODE): Define using __LIBGCC_HAS_DF_MODE__.
	(LIBGCC2_HAS_XF_MODE): Define using __LIBGCC_HAS_XF_MODE__.
	(LIBGCC2_HAS_TF_MODE): Define using __LIBGCC_HAS_TF_MODE__.
	* config/libbid/bid_gcc_intrinsics.h
	(LIBGCC2_LONG_DOUBLE_TYPE_SIZE): Do not define.
	(LIBGCC2_HAS_XF_MODE): Define using __LIBGCC_HAS_XF_MODE__.
	(LIBGCC2_HAS_TF_MODE): Define using __LIBGCC_HAS_TF_MODE__.
	* fixed-bit.h (LIBGCC2_LONG_DOUBLE_TYPE_SIZE): Do not define.
	(LIBGCC2_HAS_SF_MODE): Define using __LIBGCC_HAS_SF_MODE__.
	(LIBGCC2_HAS_DF_MODE): Define using __LIBGCC_HAS_DF_MODE__.

From-SVN: r215215

2014-09-12  Richard Biener  <rguenther@suse.de>

	PR middle-end/63237
	* gimple-fold.c (get_maxval_strlen): Gimplify string length.

	* g++.dg/torture/pr63237.C: New testcase.

From-SVN: r215212

2014-09-12  Marc Glisse  <marc.glisse@inria.fr>

gcc/
	* tree.c (integer_each_onep): New function.
	* tree.h (integer_each_onep): Declare it.
	* fold-const.c (fold_binary_loc): Use it for ~A + 1 to -A and
	-A - 1 to ~A.  Disable (X & 1) ^ 1, (X ^ 1) & 1 and ~X & 1 to
	(X & 1) == 0 for vector and complex.
gcc/testsuite/
	* gcc.dg/vec-andxor1.c: New file.

From-SVN: r215209

2014-09-12  Wilco Dijkstra  <wdijkstr@arm.com>

  * gcc/config/aarch64/aarch64.c: (cortexa57_regmove_cost): New cost table for
  A57.
  (cortexa53_regmove_cost): New cost table for A53.  Increase GP2FP/FP2GP cost
  to spilling from integer to FP registers.

From-SVN: r215208

2014-09-12  Wilco Dijkstra  <wdijkstr@arm.com>

  * gcc/config/aarch64/aarch64.c (aarch64_register_move_cost): Fix Q register
  move handling.
  (generic_regmove_cost): Undo raised FP2FP move cost as Q register moves are
  now handled correctly.

From-SVN: r215207

2014-09-12  Wilco Dijkstra  <wdijkstr@arm.com>

  * gcc/config/aarch64/aarch64.c (aarch64_register_move_cost): Add cost handling
  of CALLER_SAVE_REGS and POINTER_REGS.

From-SVN: r215206

2014-09-12  Wilco Dijkstra  <wilco.dijkstra@arm.com>

  gcc/
    * ree.c (combine_reaching_defs): Ensure inserted copy don't change the
    number of hard registers.

From-SVN: r215205

gcc/
	* config/i386/sse.md
	(define_mode_iterator VI48_AVX512VL): New.
	(define_expand "<avx512>_vternlog<mode>_maskz"): Rename from
	"avx512f_vternlog<mode>_maskz" and update mode iterator.
	(define_insn "<avx512>_vternlog<mode><sd_maskz_name>"): Rename
	from "avx512f_vternlog<mode><sd_maskz_name>" and update mode iterator.
	(define_insn "<avx512>_vternlog<mode>_mask"): Rename from
	"avx512f_vternlog<mode>_mask" and update mode iterator.
	(define_insn "<mask_codefor><avx512>_align<mode><mask_name>"): Rename
	from "<mask_codefor>avx512f_align<mode><mask_name>" and update mode
	iterator.
	(define_insn "<avx512>_<rotate>v<mode><mask_name>"): Rename from
	"avx512f_<rotate>v<mode><mask_name>" and update mode iterator.
	(define_insn "<avx512>_<rotate><mode><mask_name>"): Rename from
	"avx512f_<rotate><mode><mask_name>" and update mode iterator.
	(define_insn "clz<mode>2<mask_name>"): Use VI48_AVX512VL mode iterator.
	(define_insn "<mask_codefor>conflict<mode><mask_name>"): Ditto.


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r215203

gcc/
	* config/i386/sse.md (VI128_256): Delete.
	(define_mode_iterator VI124_256): New.
	(define_mode_iterator VI124_256_AVX512F_AVX512BW): Ditto.
	(define_expand "<code><mode>3<mask_name><round_name>"): Delete.
	(define_expand "<code><VI124_256_AVX512F_AVX512BW:mode>3"): New.
	(define_insn "*avx2_<code><VI124_256:mode>3"): Rename from
	"*avx2_<code><mode>3<mask_name><round_name>" and update mode iterator.
	(define_expand "<code><VI48_AVX512VL:mode>3_mask"): New.
	(define_insn "*avx512bw_<code><VI48_AVX512VL:mode>3<mask_name>"): Ditto.
	(define_insn "<mask_codefor><code><mode>3<mask_name>"): Update mode
	iterator.
	(define_expand "<code><VI8_AVX2:mode>3"): Update pettern generation
	in presence of AVX-512.


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r215202

gcc/
	* config/i386/sse.md
	(define_expand "<avx512>_gathersi<mode>"): Rename from
	"avx512f_gathersi<mode>".
	(define_insn "*avx512f_gathersi<mode>"): Use VI48F.
	(define_insn "*avx512f_gathersi<mode>_2"): Ditto.
	(define_expand "<avx512>_gatherdi<mode>"): Rename from
	"avx512f_gatherdi<mode>".
	(define_insn "*avx512f_gatherdi<mode>"): Use VI48F.
	(define_insn "*avx512f_gatherdi<mode>_2"): Use VI48F, add 128/256-bit
	wide versions.
	(define_expand "<avx512>_scattersi<mode>"): Rename from
	"avx512f_scattersi<mode>".
	(define_insn "*avx512f_scattersi<mode>"): Use VI48F.
	(define_expand "<avx512>_scatterdi<mode>"): Rename from
	"avx512f_scatterdi<mode>".
	(define_insn "*avx512f_scatterdi<mode>"): Use VI48F.


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r215201

gcc/
	* ira.h (ira_finish_once): Delete.
	* ira-int.h (target_ira_int::~target_ira_int): Declare.
	(target_ira_int::free_ira_costs): Likewise.
	(target_ira_int::free_register_move_costs): Likewise.
	(ira_finish_costs_once): Delete.
	* ira.c (free_register_move_costs): Replace with...
	(target_ira_int::free_register_move_costs): ...this new function.
	(target_ira_int::~target_ira_int): Define.
	(ira_init): Call free_register_move_costs as a member function rather
	than a global function.
	(ira_finish_once): Delete.
	* ira-costs.c (free_ira_costs): Replace with...
	(target_ira_int::free_ira_costs): ...this new function.
	(ira_init_costs): Call free_ira_costs as a member function rather
	than a global function.
	(ira_finish_costs_once): Delete.
	* target-globals.c (target_globals::~target_globals): Call the
	target_ira_int destructor.
	* toplev.c: Include lra.h.
	(finalize): Call lra_finish_once rather than ira_finish_once.

From-SVN: r215200

From-SVN: r215199

	* common.opt (flto-odr-type-merging): New flag.
	* ipa-deivrt.c (hash_type_name): Use ODR names for hasing if availale.
	(types_same_for_odr): Likewise.
	(odr_subtypes_equivalent_p): Likewise.
	(add_type_duplicate): Do not walk type variants.
	(register_odr_type): New function.
	* ipa-utils.h (register_odr_type): Declare.
	(odr_type_p): New function.
	* langhooks.c (lhd_set_decl_assembler_name): Do not compute
	TYPE_DECLs
	* doc/invoke.texi (-flto-odr-type-merging): Document.
	* tree.c (need_assembler_name_p): Compute ODR names when asked
	for it.
	* tree.h (DECL_ASSEMBLER_NAME): Update comment.

	* lto.c (lto_read_decls): Register ODR types.

From-SVN: r215196

	PR target/63228
	* config/i386/i386.c (ix86_option_override_internal): Also turn
	off OPTION_MASK_ABI_X32 for -m16.

From-SVN: r215194

2014-09-11  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/rs6000.md (rs6000_mftb_<mode>): Use mode iterator
	GPR instead of P.

From-SVN: r215193

2014-09-11  Marc Glisse  <marc.glisse@inria.fr>

	PR target/58757
gcc/c-family/
	* c-cppbuiltin.c (builtin_define_float_constants): Correct
	__*_DENORM_MIN__ without denormals.
gcc/
	* ginclude/float.h (FLT_TRUE_MIN, DBL_TRUE_MIN, LDBL_TRUE_MIN):
	Directly forward to __*_DENORM_MIN__.
gcc/testsuite/
	* gcc.dg/c11-true_min-1.c: New testcase.

From-SVN: r215191

gcc/ChangeLog:
2014-09-11  David Malcolm  <dmalcolm@redhat.com>

	* rtl.h (LABEL_REF_LABEL): New macro.

	* alias.c (rtx_equal_for_memref_p): Use LABEL_REF_LABEL in place
	of XEXP (, 0), where we know that we have a LABEL_REF.
	* cfgbuild.c (make_edges): Likewise.
	(purge_dead_tablejump_edges): Likewise.
	* cfgexpand.c (convert_debug_memory_address): Likewise.
	* cfgrtl.c (patch_jump_insn): Likewise.
	* combine.c (distribute_notes): Likewise.
	* cse.c (hash_rtx_cb): Likewise.
	(exp_equiv_p): Likewise.
	(fold_rtx): Likewise.
	(check_for_label_ref): Likewise.
	* cselib.c (rtx_equal_for_cselib_1): Likewise.
	(cselib_hash_rtx): Likewise.
	* emit-rtl.c (mark_label_nuses): Likewise.
	* explow.c (convert_memory_address_addr_space): Likewise.
	* final.c (output_asm_label): Likewise.
	(output_addr_const): Likewise.
	* gcse.c (add_label_notes): Likewise.
	* genconfig.c (walk_insn_part): Likewise.
	* genrecog.c (validate_pattern): Likewise.
	* ifcvt.c (cond_exec_get_condition): Likewise.
	(noce_emit_store_flag): Likewise.
	(noce_get_alt_condition): Likewise.
	(noce_get_condition): Likewise.
	* jump.c (maybe_propagate_label_ref): Likewise.
	(mark_jump_label_1): Likewise.
	(redirect_exp_1): Likewise.
	(rtx_renumbered_equal_p): Likewise.
	* lra-constraints.c (operands_match_p): Likewise.
	* reload.c (operands_match_p): Likewise.
	(find_reloads): Likewise.
	* reload1.c (set_label_offsets): Likewise.
	* reorg.c (get_branch_condition): Likewise.
	* rtl.c (rtx_equal_p_cb): Likewise.
	(rtx_equal_p): Likewise.
	* rtlanal.c (reg_mentioned_p): Likewise.
	(rtx_referenced_p): Likewise.
	(get_condition): Likewise.
	* sched-vis.c (print_value): Likewise.
	* varasm.c (const_hash_1): Likewise.
	(compare_constant): Likewise.
	(const_rtx_hash_1): Likewise.
	(output_constant_pool_1): Likewise.

From-SVN: r215190

2014-09-11  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/htm.md (tabort, tabortdc, tabortdci, tabortwc,
	tabortwci, tbegin, tcheck, tend, trechkpt, treclaim, tsr): Use xor
	instead of minus.
	* config/rs6000/vector.md (cr6_test_for_zero_reverse,
	cr6_test_for_lt_reverse): Ditto.

From-SVN: r215187

2014-09-11  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/61489
	* doc/invoke.texi ([-Wmissing-field-initializers]): Update.

/cp
2014-09-11  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/61489
	* typeck2.c (process_init_constructor_record): Do not warn about
	missing field initializer if EMPTY_CONSTRUCTOR_P (init).

/testsuite
2014-09-11  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/61489
	* g++.dg/warn/Wmissing-field-initializers-1.C: New.
	* g++.old-deja/g++.other/warn5.C: Adjust.

From-SVN: r215186

	* config/aarch64/aarch64-builtins.c (aarch64_types_unop_su_qualifiers,
	TYPES_REINTERP_SU, aarch64_types_unop_sp_qualifiers, TYPE_REINTERP_SP,
	aarch64_types_unop_us_qualifiers, TYPES_REINTERP_US,
	aarch64_types_unop_ps_qualifiers, TYPES_REINTERP_PS, BUILTIN_VD):
	Delete.

	(aarch64_fold_builtin): Remove all reinterpret cases.

	* config/aarch64/aarch64-protos.h (aarch64_simd_reinterpret): Delete.

	* config/aarch64/aarch64-simd-builtins.def (reinterpret*) : Delete.

	* config/aarch64/aarch64-simd.md (aarch64_reinterpretv8qi<mode>,
	aarch64_reinterpretv4hi<mode>, aarch64_reinterpretv2si<mode>,
	aarch64_reinterpretv2sf<mode>, aarch64_reinterpretdi<mode>,
	aarch64_reinterpretv1df<mode>, aarch64_reinterpretv16qi<mode>,
	aarch64_reinterpretv8hi<mode>, aarch64_reinterpretv4si<mode>,
	aarch64_reinterpretv4sf<mode>, aarch64_reinterpretv2di<mode>,
	aarch64_reinterpretv2df<mode>): Delete.

	* config/aarch64/aarch64.c (aarch64_simd_reinterpret): Delete.

	* config/aarch64/arm_neon.h (vreinterpret_p8_f64,
	vreinterpret_p16_f64, vreinterpret_f32_f64, vreinterpret_f64_f32,
	vreinterpret_f64_p8, vreinterpret_f64_p16, vreinterpret_f64_s8,
	vreinterpret_f64_s16, vreinterpret_f64_s32, vreinterpret_f64_u8,
	vreinterpret_f64_u16, vreinterpret_f64_u32, vreinterpret_s64_f64,
	vreinterpret_u64_f64, vreinterpret_s8_f64, vreinterpret_s16_f64,
	vreinterpret_s32_f64, vreinterpret_u8_f64, vreinterpret_u16_f64,
	vreinterpret_u32_f64): Use cast.

	* config/aarch64/iterators.md (VD_RE): Delete.

From-SVN: r215180

	* config/aarch64/arm_neon.h (aarch64_vset_lane_any): New (*2).
	(vset_lane_f32, vset_lane_f64, vset_lane_p8, vset_lane_p16,
	vset_lane_s8, vset_lane_s16, vset_lane_s32, vset_lane_s64,
	vset_lane_u8, vset_lane_u16, vset_lane_u32, vset_lane_u64,
	vsetq_lane_f32, vsetq_lane_f64, vsetq_lane_p8, vsetq_lane_p16,
	vsetq_lane_s8, vsetq_lane_s16, vsetq_lane_s32, vsetq_lane_s64,
	vsetq_lane_u8, vsetq_lane_u16, vsetq_lane_u32, vsetq_lane_u64):
	Replace inline assembler with __aarch64_vset_lane_any.

From-SVN: r215179

	* gcc.target/aarch64/vset_lane_1.c: New test.

From-SVN: r215177

gcc/

	* config/aarch64/arm_neon.h (vmull_high_lane_s16): Fix argument
	types.
	(vmull_high_lane_s32): Likewise.
	(vmull_high_lane_u16): Likewise.
	(vmull_high_lane_u32): Likewise.

From-SVN: r215176

	PR c++/63139
	* pt.c (tsubst_pack_expansion): Simplify substitution into T....
	(tsubst): Don't throw away PACK_EXPANSION_EXTRA_ARGS.

From-SVN: r215171

	PR c++/58678
	* ipa-devirt.c (ipa_devirt): Don't check DECL_COMDAT.

From-SVN: r215168

	PR libstdc++/63219
	* include/bits/regex.h (match_results::format): Remove stray template
	parameter.
	* include/bits/regex_compiler.h (_RegexTranslator::_RegexTranslator):
	Remove parameter name to avoid -Wunused-parameter warning.
	* include/bits/regex_executor.h (_State_info::_State_info): Reorder
	mem-initializers to avoid -Wreorder warning.
	* include/bits/regex_executor.tcc (_Executor::_M_word_boundary):
	Remove parameter name to avoid -Wunused-parameter warning.
	* include/bits/regex_scanner.tcc (_Scanner::_M_advance): Add braces
	to avoid -Wempty-body warning when not in debug mode.

From-SVN: r215160

	* gcc.dg/compat/struct-by-value-13_main.c (struct_by_value_13_x):
	Fix declaration.
	* gcc.dg/compat/struct-by-value-16a_main.c (struct_by_value_16a_x):
	Fix declaration.
	* gcc.dg/compat/struct-by-value-17a_main.c (struct_by_value_17a_x):
	Fix declaration.
	* gcc.dg/compat/struct-by-value-18a_main.c (struct_by_value_18a_x):
	Fix declaration.

From-SVN: r215158

	* src/powerpc/linux64.S: Emit .note.GNU-stack even when
	POWERPC64 is not defined.
	* src/powerpc/linux64_closure.S: Likewise.  Also test _CALL_ELF == 2.

From-SVN: r215155

gcc/
	PR target/63223
	* config/avr/avr.md (*tablejump.3byte-pc): New insn.
	(*tablejump): Restrict to !AVR_HAVE_EIJMP_EICALL.  Add void clobber.
	(casesi): Expand to *tablejump.3byte-pc if AVR_HAVE_EIJMP_EICALL.
libgcc/
	PR target/63223
	* config/avr/libgcc.S (__tablejump2__): Rewrite to use RAMPZ, ELPM
	and R24 as needed.  Make work for all devices and .text locations.
	(__do_global_ctors, __do_global_dtors): Use word addresses.
	(__tablejump__, __tablejump_elpm__): Remove functions.
	* t-avr (LIB1ASMFUNCS): Remove _tablejump, _tablejump_elpm.
	Add _tablejump2.
	(XICALL, XIJMP): New macros.

From-SVN: r215152

gcc/
	* config/i386/sse.md
	(define_expand "<avx512>_vpermi2var<VI48F:mode>3_maskz"): Rename from
	"avx512f_vpermi2var<mode>3_maskz" and update mode iterator.
	(define_expand "<avx512>_vpermi2var<VI2_AVX512VL:mode>3_maskz"):
	New.
	(define_insn "<avx512>_vpermi2var<VI48F:mode>3<sd_maskz_name>"): Rename
	from "avx512f_vpermi2var<mode>3<sd_maskz_name>" and update mode
	iterator.
	(define_insn "<avx512>_vpermi2var<VI2_AVX512VL:mode>3<sd_maskz_name>"):
	New.
	(define_insn "<avx512>_vpermi2var<VI48F:mode>3_mask"): Rename from
	"avx512f_vpermi2var<mode>3_mask" and update mode iterator.
	(define_insn "<avx512>_vpermi2var<VI2_AVX512VL:mode>3_mask"): New.
	(define_expand "<avx512>_vpermt2var<VI48F:mode>3_maskz"): Rename from
	"avx512f_vpermt2var<mode>3_maskz" and update mode iterator.
	(define_expand "<avx512>_vpermt2var<VI2_AVX512VL:mode>3_maskz"): New.
	(define_insn "<avx512>_vpermt2var<VI48F:mode>3<sd_maskz_name>"): Rename
	from "avx512f_vpermt2var<mode>3<sd_maskz_name>" and update mode
	iterator.
	(define_insn "<avx512>_vpermt2var<VI2_AVX512VL:mode>3<sd_maskz_name>"):
	New.
	(define_insn "<avx512>_vpermt2var<VI48F:mode>3_mask"): Rename from
	"avx512f_vpermt2var<mode>3_mask" and update mode iterator.
	(define_insn "<avx512>_vpermt2var<VI2_AVX512VL:mode>3_mask"): New.


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r215151

	* varpool.c (varpool_node::ctor_useable_for_folding_p): Do not try
	to access removed nodes.

From-SVN: r215150

	PR tree-optimization/63186
	* ipa-split.c (test_nonssa_use): Skip nonforced labels.
	(mark_nonssa_use): Likewise.
	(verify_non_ssa_vars): Verify all header blocks for label
	definitions.

	* gcc.dg/pr63186.c: New testcase.

From-SVN: r215149

gcc/
	* config/i386/sse.md
	(define_mode_attr avx2_avx512): Rename from avx2_avx512bw.
	(define_mode_iterator VI48F_256_512): Extend to AVX-512VL.
	(define_insn "<avx2_avx512>_permvar<mode><mask_name>"): Rename from
	"<avx2_avx512f>_permvar<mode><mask_name>".
	(define_insn "<avx512>_permvar<mode><mask_name>"): New.
	(define_insn "<avx2_avx512>_ashrv<VI48_AVX512F_AVX512VL:mode><mask_name>"):
	Rename from "<avx2_avx512f>_ashrv<mode><mask_name>".
	(define_insn "<avx2_avx512>_ashrv<VI2_AVX512VL:mode><mask_name>"):
	Ditto.
	(define_insn "<avx2_avx512>_<shift_insn>v<VI48_AVX512F:mode><mask_name>"):
	Rename from "<avx2_avx512bw>_<shift_insn>v<mode><mask_name>".
	(define_insn "<avx2_avx512>_<shift_insn>v<VI2_AVX512VL:mode><mask_name>"):
	Rename from "<avx2_avx512bw>_<shift_insn>v<mode><mask_name>".


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r215148

From-SVN: r215147

2014-09-10  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/vsx.md (vsx_fmav4sf4): Use correct constraints for
	V2DF, V4SF, DF, and DI modes.
	(vsx_fmav2df2): Likewise.
	(vsx_float_fix_<mode>2): Likewise.
	(vsx_reduc_<VEC_reduc_name>_v2df_scalar): Likewise.

From-SVN: r215138

From-SVN: r215136

	* gcc.target/i386/i386.exp: Only run vect-args.c tests
	if runtest_file_p says they should be run.

From-SVN: r215135

	PR c++/61659
	* decl.c (grokfndecl): Don't set DECL_COMDAT on static inlines.
	(duplicate_decls, start_decl): Likewise.
	* pt.c (check_explicit_specialization): Likewise.
	(push_template_decl_real): Or static templates.

From-SVN: r215134

gcc/ChangeLog:
2014-09-10  David Malcolm  <dmalcolm@redhat.com>

	* final.c (this_is_asm_operands): Strengthen this variable from
	rtx to const rtx_insn *.
	* output.h (this_is_asm_operands): Likewise.
	* rtl-error.c (location_for_asm): Strengthen param "insn" from
	const_rtx to const rtx_insn *.
	(diagnostic_for_asm): Likewise.
	* rtl-error.h (error_for_asm): Likewise.
	(warning_for_asm): Likewise.

From-SVN: r215133

gcc/ChangeLog:
2014-09-10  David Malcolm  <dmalcolm@redhat.com>

	* genextract.c (print_header): When writing out insn_extract to
	insn-extract.c, strengthen the param "insn" from rtx to rtx_insn *.
	* recog.h (insn_extract): Strengthen the param from rtx to
	rtx_insn *.

From-SVN: r215132