1. 26 Apr, 2018 18 commits
  2. 25 Apr, 2018 17 commits
  3. 24 Apr, 2018 5 commits
    • re PR fortran/85520 (Out of memory when declaring a character with len << 0) · 58da192e
      2018-04-24  Steven G. Kargl  <kargl@gcc.gnu.org>
      
      	PR fortran/85520
      	* decl.c (gfc_match_char_spec): Check for negative length and set to 0.
      
      2018-04-24  Steven G. Kargl  <kargl@gcc.gnu.org>
      
      	PR fortran/85520
      	* gfortran.dg/pr85520.f90: New test.
      
      From-SVN: r259623
      Steven G. Kargl committed
    • rs6000: Fix __powikf2 and __abskf2 spelling · 08417efa
      Both of these libfuncs had a "tkf" misspelling, which caused
      gcc.target/powerpc/pr85456.c to fail (there is no test for __abskf2).
      
      
      	* config/rs6000/rs6000.c (init_float128_ieee): Fix spelling mistakes
      	in __abskf2 and __powikf2.
      
      From-SVN: r259622
      Segher Boessenkool committed
    • x86: Update __CET__ check · ffc2fc06
      __CET__ has been changed by revision 259522:
      
      commit d59cfa9a4064339cf2bd2da828c4c133f13e57f0
      Author: hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4>
      Date:   Fri Apr 20 13:30:13 2018 +0000
      
          Define __CET__ for -fcf-protection and remove -mibt
      
      to
      
          (__CET__ & 1) != 0: -fcf-protection=branch or -fcf-protection=full
          (__CET__ & 2) != 0: -fcf-protection=return or -fcf-protection=full
      
      We should check (__CET__ & 2) != 0 for shadow stack.
      
      libgcc/
      
      	* config/i386/linux-unwind.h: Add (__CET__ & 2) != 0 check
      	when including "config/i386/shadow-stack-unwind.h".
      
      libitm/
      
      	* config/x86/sjlj.S (_ITM_beginTransaction): Add
      	(__CET__ & 2) != 0 check for shadow stack.
      	(GTM_longjmp): Likewise.
      
      From-SVN: r259621
      H.J. Lu committed
    • x86/CET: Add -fcf-protection to STAGE4_CFLAGS · e59133c3
      Since profiledbootstrap uses
      
      STAGEfeedback_CFLAGS = $(STAGE4_CFLAGS) -fprofile-use
      
      add
      
      STAGE4_CFLAGS += -fcf-protection -mcet
      
      to bootstrap-cet.mk to support profiledbootstrap with CET.
      
      	PR bootstrap/85490
      	* bootstrap-cet.mk (STAGE4_CFLAGS): New.
      
      From-SVN: r259620
      H.J. Lu committed
    • [AArch64] PR target/85512: Tighten SIMD right shift immediate constraints · 0603375c
      In this testcase it is possible to generate an invalid SISD shift of zero:
      Error: immediate value out of range 1 to 64 at operand 3 -- `sshr v9.2s,v0.2s,0'
      
      The SSHR and USHR instructions require a shift from 1 up to the element size.
      However our constraints on the scalar shifts that generate these patterns
      allow a shift amount of zero as well. The pure GP-reg ASR and LSR instructions allow a shift amount of zero.
      
      It is unlikely that a shift of zero will survive till the end of compilation, but it's not impossible, as this PR shows.
      
      The patch tightens up the constraints in the offending patterns by adding two new constraints
      that allow shift amounts [1,32] and [1,64] and using them in *aarch64_ashr_sisd_or_int_<mode>3
      and *aarch64_lshr_sisd_or_int_<mode>3.
      The left-shift SISD instructions SHL and USHL allow a shift amount of zero so don't need adjustment
      The vector shift patterns that map down to SSHR and USHR already enforce the correct immediate range. 
      
              PR target/85512
              * config/aarch64/constraints.md (Usg, Usj): New constraints.
              * config/aarch64/iterators.md (cmode_simd): New mode attribute.
              * config/aarch64/aarch64.md (*aarch64_ashr_sisd_or_int_<mode>3):
              Use the above on operand 2.  Reindent.
              (*aarch64_lshr_sisd_or_int_<mode>3): Likewise.
      
              * gcc.dg/pr85512.c: New test.
      
      From-SVN: r259614
      Kyrylo Tkachov committed