libraries.

        * config.host (tilepro*-*-linux*): Add t-slibgcc-libgcc.

From-SVN: r242615

From-SVN: r242613

	PR c++/68180
	* g++.dg/cpp1y/pr68180.C: Add -Wno-psabi as dg-additional-options.

From-SVN: r242610

	PR middle-end/78419
	* multiple_target.c (get_attr_len): Start with argnum and increment
	argnum on every arg.  Use strchr in a loop instead of counting commas
	manually.
	(get_attr_str): Increment argnum for every comma in the string.
	(separate_attrs): Use for instead of while loop, simplify.
	(expand_target_clones): Rename defenition argument to definition.
	Free attrs and attr_str even when diagnosing errors.  Temporarily
	change input_location around targetm.target_option.valid_attribute_p
	calls.  Don't emit warning or errors if that function fails.

	* gcc.target/i386/pr78419.c: New test.

From-SVN: r242608

	PR c++/77285
	* mangle.c (mangle_tls_init_fn, mangle_tls_wrapper_fn): Call
	check_abi_tags.

	* g++.dg/tls/pr77285-1.C: New test.
	* g++.dg/tls/pr77285-2.C: New test.

From-SVN: r242607

	* dwarf2out.c (size_of_discr_list): Fix typo in function comment.

	PR debug/78191
	* dwarf2out.c (abbrev_opt_base_type_end): New variable.
	(die_abbrev_cmp): Sort dies with die_abbrev smaller than
	abbrev_opt_base_type_end only by increasing die_abbrev, before
	any other dies.
	(optimize_abbrev_table): Don't change abbrev numbers of
	base types and CU or optimize implicit consts in them if
	calc_base_type_die_sizes has been called during build_abbrev_table.
	(calc_base_type_die_sizes): If abbrev_opt_start, set
	abbrev_opt_base_type_end to one plus largest base type's
	die_abbrev.

From-SVN: r242606

	PR target/25112
	* config/m68k/m68k.c (moveq feeding equality comparison): New
	peepholes.
	* config/m68k/predicates.md (addq_subq_operand): New predicate.
	(equality_comparison_operator): Likewise.

	PR target/25112
	* gcc.target/m68k/pr25112: New test.

From-SVN: r242605

	* semantics.c (finish_compound_literal): Call digest_init_flags.
	* typeck2.c (digest_init_flags): Add complain parm.
	(store_init_value): Pass it.

From-SVN: r242603

        * gcc.dg/tree-ssa/pr71179.c: Prune ABI message.
        * gcc.dg/tree-ssa/ssa-fre-55.c: Same.

From-SVN: r242602

gcc/
	* rtlanal.c (load_extend_op): Move to...
	* rtl.h: ...here and make inline.

From-SVN: r242601

    
    This doesn't change any actual code, it just starts using the Go
    definition of the schedt type and the sched variable rather than the C
    definitions.
    
    The schedt type is tweaked slightly for gccgo.  We aren't going to
    release goroutine stacks, so we don't need separate gfreeStack and
    gfreeNostack lists.  We only have one size of defer function, so we
    don't need a list of 5 different pools.
    
    Reviewed-on: https://go-review.googlesource.com/33364

From-SVN: r242600

2016-11-18  Terry Guo  <terry.guo@arm.com>
            Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    * common/config/arm/arm-common.c (arm_target_thumb_only): New function.
    * config/arm/arm-opts.h: Include arm-flags.h.
    (struct arm_arch_core_flag): Define.
    (arm_arch_core_flags): Define.
    * config/arm/arm-protos.h: Include arm-flags.h
    (FL_NONE, FL_ANY, FL_CO_PROC, FL_ARCH3M, FL_MODE26, FL_MODE32,
    FL_ARCH4, FL_ARCH5, FL_THUMB, FL_LDSCHED, FL_STRONG, FL_ARCH5E,
    FL_XSCALE, FL_ARCH6, FL_VFPV2, FL_WBUF, FL_ARCH6K, FL_THUMB2, FL_NOTM,
    FL_THUMB_DIV, FL_VFPV3, FL_NEON, FL_ARCH7EM, FL_ARCH7, FL_ARM_DIV,
    FL_ARCH8, FL_CRC32, FL_SMALLMUL, FL_NO_VOLATILE_CE, FL_IWMMXT,
    FL_IWMMXT2, FL_ARCH6KZ, FL2_ARCH8_1, FL2_ARCH8_2, FL2_FP16INST,
    FL_TUNE, FL_FOR_ARCH2, FL_FOR_ARCH3, FL_FOR_ARCH3M, FL_FOR_ARCH4,
    FL_FOR_ARCH4T, FL_FOR_ARCH5, FL_FOR_ARCH5T, FL_FOR_ARCH5E,
    FL_FOR_ARCH5TE, FL_FOR_ARCH5TEJ, FL_FOR_ARCH6, FL_FOR_ARCH6J,
    FL_FOR_ARCH6K, FL_FOR_ARCH6Z, FL_FOR_ARCH6ZK, FL_FOR_ARCH6KZ,
    FL_FOR_ARCH6T2, FL_FOR_ARCH6M, FL_FOR_ARCH7, FL_FOR_ARCH7A,
    FL_FOR_ARCH7VE, FL_FOR_ARCH7R, FL_FOR_ARCH7M, FL_FOR_ARCH7EM,
    FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A, FL2_FOR_ARCH8_2A, FL_FOR_ARCH8M_BASE,
    FL_FOR_ARCH8M_MAIN, arm_feature_set, ARM_FSET_MAKE,
    ARM_FSET_MAKE_CPU1, ARM_FSET_MAKE_CPU2, ARM_FSET_CPU1, ARM_FSET_CPU2,
    ARM_FSET_EMPTY, ARM_FSET_ANY, ARM_FSET_HAS_CPU1, ARM_FSET_HAS_CPU2,
    ARM_FSET_HAS_CPU, ARM_FSET_ADD_CPU1, ARM_FSET_ADD_CPU2,
    ARM_FSET_DEL_CPU1, ARM_FSET_DEL_CPU2, ARM_FSET_UNION, ARM_FSET_INTER,
    ARM_FSET_XOR, ARM_FSET_EXCLUDE, ARM_FSET_IS_EMPTY,
    ARM_FSET_CPU_SUBSET): Move to ...
    * config/arm/arm-flags.h: This new file.
    * config/arm/arm.h (TARGET_MODE_SPEC_FUNCTIONS): Define.
    (EXTRA_SPEC_FUNCTIONS): Add TARGET_MODE_SPEC_FUNCTIONS to its value.
    (TARGET_MODE_SPECS): Define.
    (DRIVER_SELF_SPECS): Add TARGET_MODE_SPECS to its value.

    gcc/testsuite/
    * gcc.target/arm/optional_thumb-1.c: New test.
    * gcc.target/arm/optional_thumb-2.c: New test.
    * gcc.target/arm/optional_thumb-3.c: New test.

From-SVN: r242597

2016-11-18  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    * config/arm/arm-protos.h (FL_NONE, FL_ANY, FL_CO_PROC, FL_ARCH3M,
    FL_MODE26, FL_MODE32, FL_ARCH4, FL_ARCH5, FL_THUMB, FL_LDSCHED,
    FL_STRONG, FL_ARCH5E, FL_XSCALE, FL_ARCH6, FL_VFPV2, FL_WBUF,
    FL_ARCH6K, FL_THUMB2, FL_NOTM, FL_THUMB_DIV, FL_VFPV3, FL_NEON,
    FL_ARCH7EM, FL_ARCH7, FL_ARM_DIV, FL_ARCH8, FL_CRC32, FL_SMALLMUL,
    FL_NO_VOLATILE_CE, FL_IWMMXT, FL_IWMMXT2, FL_ARCH6KZ, FL2_ARCH8_1,
    FL2_ARCH8_2, FL2_FP16INST): Reindent comment, add final dot when
    missing and make value unsigned.
    (arm_feature_set): Use unsigned entries instead of unsigned long.

From-SVN: r242596

2016-11-18  Toma Tabacu  <toma.tabacu@imgtec.com>

	* MAINTAINERS (Write After Approval): Add myself.

From-SVN: r242595

    
    Reviewed-on: https://go-review.googlesource.com/33363

From-SVN: r242594

    
    They were removed from the master Go library in 2012
    (https://golang.org/cl/5979046) but somehow that was not reflected here.
    
    Reviewed-on: https://go-review.googlesource.com/33391

From-SVN: r242592

The attached patch makes the htm tests on s390 less sensitive to
spurious abort.  Please check the commit comment for details.  The
modified tests have been run once on a zEC12.

gcc/ChangeLog:

2016-11-18  Dominik Vogt  <vogt@linux.vnet.ibm.com>

	* config/rs6000/rs6000.c (rs6000_stack_info): PR/77359: Properly align
	local variables in functions calling alloca.  Also update the ASCII
	drawings
	* config/rs6000/rs6000.h (STARTING_FRAME_OFFSET, STACK_DYNAMIC_OFFSET):
	PR/77359: Likewise.
	* config/rs6000/aix.h (STARTING_FRAME_OFFSET, STACK_DYNAMIC_OFFSET):
	PR/77359: Copy AIX specific versions of the rs6000.h macros to aix.h.

From-SVN: r242591

The patch got reverted after hitting PR77359 which turned out to be a
rs6000 backend problem.  Reapplying after the PR got fixed.

gcc/ChangeLog:

2016-11-18  Dominik Vogt  <vogt@linux.vnet.ibm.com>

	Re-apply after PR bootstrap/77359 is fixed:
	2016-08-23  Dominik Vogt  <vogt@linux.vnet.ibm.com>

        * explow.c (get_dynamic_stack_size): Take known alignment of stack
        pointer + STACK_DYNAMIC_OFFSET into account when calculating the
        size needed.

--This line, and those below, will be
ignored--

M    gcc/ChangeLog
M    gcc/explow.c

From-SVN: r242590

gcc/ChangeLog:

2016-11-18  Dominik Vogt  <vogt@linux.vnet.ibm.com>

	* config/rs6000/rs6000.c (rs6000_stack_info): PR/77359: Properly align
	local variables in functions calling alloca.  Also update the ASCII
	drawings
	* config/rs6000/rs6000.h (STARTING_FRAME_OFFSET, STACK_DYNAMIC_OFFSET):
	PR/77359: Likewise.
	* config/rs6000/aix.h (STARTING_FRAME_OFFSET, STACK_DYNAMIC_OFFSET):
	PR/77359: Copy AIX specific versions of the rs6000.h macros to aix.h.

From-SVN: r242589

gcc/testsuite/

	* gcc.target/mips/inline-memcpy-1.c (dg-options): Add
	(REQUIRES_STDLIB).
	* gcc.target/mips/inline-memcpy-2.c: Ditto.
	* gcc.target/mips/inline-memcpy-3.c: Ditto.
	* gcc.target/mips/inline-memcpy-4.c: Ditto.
	* gcc.target/mips/inline-memcpy-5.c: Ditto.
	* gcc.target/mips/loongson-shift-count-truncated-1.c: Ditto.
	* gcc.target/mips/loongson-simd.c: Ditto.
	* gcc.target/mips/memcpy-1.c: Ditto.
	* gcc.target/mips/mips-3d-1.c: Ditto.
	* gcc.target/mips/mips-3d-2.c: Ditto.
	* gcc.target/mips/mips-3d-3.c: Ditto.
	* gcc.target/mips/mips-3d-4.c: Ditto.
	* gcc.target/mips/mips-3d-5.c: Ditto.
	* gcc.target/mips/mips-3d-6.c: Ditto.
	* gcc.target/mips/mips-3d-7.c: Ditto.
	* gcc.target/mips/mips-3d-8.c: Ditto.
	* gcc.target/mips/mips-3d-9.c: Ditto.
	* gcc.target/mips/mips-ps-1.c: Ditto.
	* gcc.target/mips/mips-ps-2.c: Ditto.
	* gcc.target/mips/mips-ps-3.c: Ditto.
	* gcc.target/mips/mips-ps-4.c: Ditto.
	* gcc.target/mips/mips-ps-6.c: Ditto.
	* gcc.target/mips/mips16-attributes.c: Ditto.
	* gcc.target/mips/mips32-dsp-run.c: Ditto.
	* gcc.target/mips/mips32-dsp.c: Ditto.
	* gcc.target/mips/save-restore-1.c: Ditto.
	* gcc.target/mips/mips.exp (mips_option_groups): Add stdlib.
	(mips_preprocess): Add ignore_output argument that when set
	will not return the pre-processed output.
	(mips_arch_info): Update arguments for the call to
	mips_preprocess.
	(mips-dg-init): Ditto.
	(mips-dg-options): Check if a test having test option
	(REQUIRES_STDLIB) has the required sysroot support for
	the current test options.

Co-Authored-By: Toma Tabacu <toma.tabacu@imgtec.com>

From-SVN: r242587

This change makes the code less sensitive to the exact type of the mode,
i.e. it forces a conversion where necessary.  This becomes important
when wrappers like scalar_int_mode and scalar_mode can also be used
instead of machine_mode.

Using rtx_mode_t also abstracts away the representation.  The fact that
it's a std::pair rather than a custom class isn't important to users of
the interface.

gcc/
2016-11-18  Richard Sandiford  <richard.sandiford@arm.com>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

	* combine.c (try_combine): Use rtx_mode_t instead of std::make_pair.
	* dwarf2out.c (mem_loc_descriptor, loc_descriptor): Likewise.
	(add_const_value_attribute): Likewise.
	* explow.c (plus_constant): Likewise.
	* expmed.c (expand_mult, make_tree): Likewise.
	* expr.c (convert_modes): Likewise.
	* loop-doloop.c (doloop_optimize): Likewise.
	* postreload.c (reload_cse_simplify_set): Likewise.
	* simplify-rtx.c (simplify_const_unary_operation): Likewise.
	(simplify_binary_operation_1, simplify_const_binary_operation):
	(simplify_const_relational_operation, simplify_immed_subreg): Likewise.
	* wide-int.h: Update documentation to recommend rtx_mode_t
	instead of std::make_pair.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r242586

This may no longer be necessary with the current version
of the SVE patches, but it does at least make things consistent
with the TYPE_MODE/SET_TYPE_MODE split.

gcc/ada/
2016-11-16  Richard Sandiford  <richard.sandiford@arm.com>
 	    Alan Hayward  <alan.hayward@arm.com>
 	    David Sherwood  <david.sherwood@arm.com>

	* gcc-interface/utils.c (create_label_decl): Use SET_DECL_MODE.

gcc/c/
2016-11-16  Richard Sandiford  <richard.sandiford@arm.com>
 	    Alan Hayward  <alan.hayward@arm.com>
 	    David Sherwood  <david.sherwood@arm.com>

	* c-decl.c (merge_decls): Use SET_DECL_MODE.
	(make_label, finish_struct): Likewise.

gcc/cp/
2016-11-16  Richard Sandiford  <richard.sandiford@arm.com>
 	    Alan Hayward  <alan.hayward@arm.com>
 	    David Sherwood  <david.sherwood@arm.com>

	* class.c (finish_struct_bits): Use SET_DECL_MODE.
	(build_base_field_1, layout_class_type, finish_struct_1): Likewise.
	* decl.c (make_label_decl): Likewise.
	* pt.c (tsubst_decl): Likewise.

gcc/fortran/
2016-11-16  Richard Sandiford  <richard.sandiford@arm.com>
 	    Alan Hayward  <alan.hayward@arm.com>
 	    David Sherwood  <david.sherwood@arm.com>

	* trans-common.c (build_common_decl): Use SET_DECL_MODE.
	* trans-decl.c (gfc_build_label_decl): Likewise.
	* trans-types.c (gfc_get_array_descr_info): Likewise.

gcc/lto/
2016-11-16  Richard Sandiford  <richard.sandiford@arm.com>
 	    Alan Hayward  <alan.hayward@arm.com>
 	    David Sherwood  <david.sherwood@arm.com>

	* lto.c (offload_handle_link_vars): Use SET_DECL_MODE.

gcc/
2016-11-16  Richard Sandiford  <richard.sandiford@arm.com>
 	    Alan Hayward  <alan.hayward@arm.com>
 	    David Sherwood  <david.sherwood@arm.com>

	* tree.h (SET_DECL_MODE): New macro.
	* cfgexpand.c (avoid_deep_ter_for_debug): Use SET_DECL_MODE.
	(expand_gimple_basic_block): Likewise.
	* function.c (split_complex_args): Likeise.
	* ipa-prop.c (ipa_modify_call_arguments): Likewise.
	* omp-simd-clone.c (ipa_simd_modify_stmt_ops): Likewise.
	* stor-layout.c (layout_decl, relayout_decl): Likewise.
	(finish_bitfield_representative): Likewise.
	* tree.c (make_node_stat): Likewise.
	* tree-inline.c (remap_ssa_name): Likewise.
	(tree_function_versioning): Likewise.
	* tree-into-ssa.c (rewrite_debug_stmt_uses): Likewise.
	* tree-sra.c (sra_ipa_reset_debug_stmts): Likewise.
	* tree-ssa-ccp.c (optimize_atomic_bit_test_and): Likewise.
	* tree-ssa-loop-ivopts.c (remove_unused_ivs): Likewise.
	* tree-ssa.c (insert_debug_temp_for_var_def): Likewise.
	* tree-streamer-in.c (unpack_ts_decl_common_value_fields): Likewise.
	* varasm.c (make_debug_expr_from_rtl): Likewise.

libcc1/
2016-11-16  Richard Sandiford  <richard.sandiford@arm.com>
 	    Alan Hayward  <alan.hayward@arm.com>
 	    David Sherwood  <david.sherwood@arm.com>

	* plugin.cc (plugin_build_add_field): Use SET_DECL_MODE.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r242585

For code like the testcase in PR71785 GCC factors all the indirect branches
to a single dispatcher that then everything jumps to.  This is because
having many indirect branches with each many jump targets does not scale
in large parts of the compiler.  Very late in the pass pipeline (right
before peephole2) the indirect branches are then unfactored again, by
the duplicate_computed_gotos pass.

This pass works by replacing branches to such a common dispatcher by a
copy of the dispatcher.  For code like this testcase this does not work
so well: most cases do a single addition instruction right before the
dispatcher, but not all, and we end up with only two indirect jumps: the
one without the addition, and the one with the addition in its own basic
block, and now everything else jumps _there_.

This patch rewrites the algorithm to deal with this.  It also makes it
simpler: it does not need the "candidates" array anymore, it does not
need RTL layout mode, it does not need cleanup_cfg, and it does not
need to keep track of what blocks it already visited.


	PR rtl-optimization/71785
	* bb-reorder.c (maybe_duplicate_computed_goto): New function.
	(duplicate_computed_gotos): New function.
	(pass_duplicate_computed_gotos::execute): Rewrite.

From-SVN: r242584

Correct gcc/go/gofrontend/lex.cc and libgo/aclocal.m4 to the versions
in the gofrontend repo, which is supposed to be the master copy.

Remove a few files in libgo that somehow were not deleted in the past.

From-SVN: r242583

Update a few binary files that were changed in the master gc repo,
copied into the gofrontend repo, but not correctly copied into the GCC
repo.  The changes are all minor and do not affect any actual tests.
Two instances of "http" changed to "https", and two timestamps were
zeroed out.

From-SVN: r242582

From-SVN: r242581

    
    As we move toward the Go 1.7 garbage collector, it's essential that all
    allocation of values that can contain Go pointers be done using the
    correct type descriptor.  That is simplest if we do all such allocation
    in Go code.  This rewrites the code that converts from a Go type to a
    libffi CIF into Go.
    
    Reviewed-on: https://go-review.googlesource.com/33353

From-SVN: r242578

	PR middle-end/38219
	* gcc.dg/tree-ssa/vrp47.c: Do not run on m68k.

From-SVN: r242576

re PR target/47192 (m68k target - gcc uses stack frame after it has been unlinked when compiling with -Os)

	PR target/47192
	* config/m68k/m68k.c (m68k_expand_epilogue): Emit a scheduling
	barrier prior to deallocating the stack.

	PR target/47192
	* gcc.target/m68k/pr47192.c: New test.

From-SVN: r242575

2016-11-17  Toma Tabacu  <toma.tabacu@imgtec.com>

	* gcc.target/mips/branch-cost-1.c (dg-options): Use (HAS_MOVN)
	instead of isa>=4, in order to downgrade to R5.

From-SVN: r242574

	* call.c (build_over_call): Don't set CALL_FROM_THUNK_P here.
	(build_call_a): Set it here, and don't insert EMPTY_CLASS_EXPR.
	(convert_like_real) [ck_rvalue]: Also pass non-addressable
	types along directly.

From-SVN: r242573

In the case where we access a single bit from a value and use this in a
EQ/NE comparison, GCC will convert this into a sign-extend and GE/LT
comparison.

Normally this would be fine, however, if the value is in CMEM memory,
then we don't have a sign-extending load available (using the special
short CMEM load instructions), and instead we end up using a long form
load with LIMM, which is less efficient.

This peephole optimisation looks for the sign-extend followed by GE/LT
pattern and converts this back into a load and EQ/NE comparison.

gcc/ChangeLog:

	* config/arc/arc.md (cmem bit/sign-extend peephole2): New peephole
	to make better use of cmem loads in the case where a single bit is
	being accessed.
	* config/arc/predicates.md (ge_lt_comparison_operator): New
	predicate.

gcc/testsuite/ChangeLog:

	* gcc.target/arc/cmem-bit-1.c: New file.
	* gcc.target/arc/cmem-bit-2.c: New file.
	* gcc.target/arc/cmem-bit-3.c: New file.
	* gcc.target/arc/cmem-bit-4.c: New file.

From-SVN: r242572

gcc/

2016-11-17  Andrew Senkevich <andrew.senkevich@intel.com>

	* config/i386/i386.c (processor_features): Add F_AVX5124VNNIW,
	F_AVX5124FMAPS.
	(isa_names_table): Handle new features.

gcc/testsuite/

2016-11-17  Andrew Senkevich <andrew.senkevich@intel.com>

	* gcc.target/i386/builtin_target.c: Handle new "avx5124vnniw",
	"avx5124fmaps".
	* gcc.target/i386/funcspec-56.inc: Test new attributes.

libgcc/

2016-11-17  Andrew Senkevich <andrew.senkevich@intel.com>

	* config/i386/cpuinfo.c (processor_features): Add
	FEATURE_AVX5124VNNIW, FEATURE_AVX5124FMAPS.

From-SVN: r242570

This requires additional patch for register allocator from Vladimir
Makarov.

gcc/

2016-11-17  Kirill Yukhin  <kirill.yukhin@gmail.com>
	    Andrew Senkevich <andrew.senkevich@intel.com>

	* common/config/i386/i386-common.c
	(OPTION_MASK_ISA_AVX5124FMAPS_SET,
	OPTION_MASK_ISA_AVX5124FMAPS_UNSET,
	OPTION_MASK_ISA_AVX5124VNNIW_SET,
	OPTION_MASK_ISA_AVX5124VNNIW_UNSET): New.
	(ix86_handle_option): Handle OPT_mavx5124fmaps,
	OPT_mavx5124vnniw.
	* config.gcc: Add avx5124fmapsintrin.h, avx5124vnniwintrin.h.
	* config/i386/avx5124fmapsintrin.h: New file.
	* config/i386/avx5124vnniwintrin.h: Ditto.
	* config/i386/constraints.md (h): New constraint.
	* config/i386/cpuid.h: (bit_AVX5124VNNIW,
	bit_AVX5124FMAPS): New.
	* config/i386/driver-i386.c (host_detect_local_cpu):
	Detect avx5124fmaps, avx5124vnniw.
	* config/i386/i386-builtin-types.def: Add types
	V16SF_FTYPE_V16SF_V16SF_V16SF_V16SF_V16SF_PCV4SF_V16SF_UHI,
	V16SF_FTYPE_V16SF_V16SF_V16SF_V16SF_V16SF_PCV4SF,
	V4SF_FTYPE_V4SF_V4SF_V4SF_V4SF_V4SF_PCV4SF,
	V4SF_FTYPE_V4SF_V4SF_V4SF_V4SF_V4SF_PCV4SF_V4SF_UQI,
	V16SI_FTYPE_V16SI_V16SI_V16SI_V16SI_V16SI_PCV4SI,
	V16SI_FTYPE_V16SI_V16SI_V16SI_V16SI_V16SI_PCV4SI_V16SI_UHI.
	* config/i386/i386-builtin.def (__builtin_ia32_4fmaddps_mask,
	__builtin_ia32_4fmaddps, __builtin_ia32_4fmaddss,
	__builtin_ia32_4fmaddss_mask, __builtin_ia32_4fnmaddps_mask,
	__builtin_ia32_4fnmaddps, __builtin_ia32_4fnmaddss,
	__builtin_ia32_4fnmaddss_mask, __builtin_ia32_vp4dpwssd,
	__builtin_ia32_vp4dpwssd_mask, __builtin_ia32_vp4dpwssds,
	__builtin_ia32_vp4dpwssds_mask): New.
	* config/i386/i386-c.c (ix86_target_macros_internal):
	Define __AVX5124FMAPS__, __AVX5124VNNIW__.
	* config/i386/i386-modes.def: Fixed comment typos, added new
	modes (VECTOR_MODES (FLOAT, 256), VECTOR_MODE (INT, SI, 64)).
	* config/i386/i386.c (ix86_target_string): Add -mavx5124fmaps,
	-mavx5124vnniw.
	(PTA_AVX5124FMAPS, PTA_AVX5124VNNIW): Define.
	(ix86_option_override_internal): Handle new options.
	(ix86_valid_target_attribute_inner_p): Add avx5124fmaps,
	avx5124vnniw.
	(ix86_expand_builtin): Handle new builtins.
	(ix86_additional_allocno_class_p): New.
	* config/i386/i386.h (TARGET_AVX5124FMAPS,
	TARGET_AVX5124FMAPS_P,
	TARGET_AVX5124VNNIW,
	TARGET_AVX5124VNNIW_P): Define.
	(reg_class): Add MOD4_SSE_REGS.
	(MOD4_SSE_REG_P, MOD4_SSE_REGNO_P): New.
	* config/i386/i386.opt: Add mavx5124fmaps, mavx5124vnniw.
	* config/i386/immintrin.h: Include avx5124fmapsintrin.h,
	avx5124vnniwintrin.h.
	* config/i386/sse.md (unspec): Add UNSPEC_VP4FMADD,
	UNSPEC_VP4FNMADD,
	UNSPEC_VP4DPWSSD, UNSPEC_VP4DPWSSDS.
	(define_mode_iterator IMOD4): New.
	(define_mode_attr imod4_narrow): Ditto.
	(define_insn "mov<mode>"): Ditto.
	(define_insn "avx5124fmaddps_4fmaddps"): Ditto.
	(define_insn "avx5124fmaddps_4fmaddps_mask"): Ditto.
	(define_insn "avx5124fmaddps_4fmaddps_maskz"): Ditto.
	(define_insn "avx5124fmaddps_4fmaddss"): Ditto.
	(define_insn "avx5124fmaddps_4fmaddss_mask"): Ditto.
	(define_insn "avx5124fmaddps_4fmaddss_maskz"): Ditto.
	(define_insn "avx5124fmaddps_4fnmaddps"): Ditto.
	(define_insn "avx5124fmaddps_4fnmaddps_mask"): Ditto.
	(define_insn "avx5124fmaddps_4fnmaddps_maskz"): Ditto.
	(define_insn "avx5124fmaddps_4fnmaddss"): Ditto.
	(define_insn "avx5124fmaddps_4fnmaddss_mask"): Ditto.
	(define_insn "avx5124fmaddps_4fnmaddss_maskz"): Ditto.
	(define_insn "avx5124vnniw_vp4dpwssd"): Ditto.
	(define_insn "avx5124vnniw_vp4dpwssd_mask"): Ditto.
	(define_insn "avx5124vnniw_vp4dpwssd_maskz"): Ditto.
	(define_insn "avx5124vnniw_vp4dpwssds"): Ditto.
	(define_insn "avx5124vnniw_vp4dpwssds_mask"): Ditto.
	(define_insn "avx5124vnniw_vp4dpwssds_maskz"): Ditto.
	* init-regs.c (initialize_uninitialized_regs): Add emit_clobber call.
	* genmodes.c (mode_size_inline): Extend return type.
	* machmode.h (mode_size, mode_base_align): Extend type.

gcc/testsuite/

2016-11-17  Kirill Yukhin  <kirill.yukhin@gmail.com>
	    Andrew Senkevich <andrew.senkevich@intel.com>

	* gcc.target/i386/avx5124fmadd-v4fmaddps-1.c: New test.
	* gcc.target/i386/avx5124fmadd-v4fmaddps-2.c: Ditto.
	* gcc.target/i386/avx5124fmadd-v4fmaddss-1.c: Ditto.
	* gcc.target/i386/avx5124fmadd-v4fnmaddps-1.c: Ditto.
	* gcc.target/i386/avx5124fmadd-v4fnmaddps-2.c: Ditto.
	* gcc.target/i386/avx5124fmadd-v4fnmaddss-1.c: Ditto.
	* gcc.target/i386/avx5124fmaps-check.h: Ditto.
	* gcc.target/i386/avx5124vnniw-check.h: Ditto.
	* gcc.target/i386/avx5124vnniw-vp4dpwssd-1.c: Ditto.
	* gcc.target/i386/avx5124vnniw-vp4dpwssd-2.c: Ditto.
	* gcc.target/i386/avx5124vnniw-vp4dpwssds-1.c: Ditto.
	* gcc.target/i386/avx5124vnniw-vp4dpwssds-2.c: Ditto.
	* gcc.target/i386/avx512f-helper.h: Add avx5124fmaps-check.h,
	avx5124vnniw-check.h.
	* gcc.target/i386/i386.exp (check_effective_target_avx5124fmaps,
	check_effective_target_avx5124vnniw): New.
	* gcc.target/i386/m128-check.h (ESP_FLOAT, ESP_DOUBLE):
	Set under ifndef.
	* gcc.target/i386/sse-12.c: Add -mavx5124fmaps, -mavx5124vnniw.
	* gcc.target/i386/sse-13.c: Ditto.
	* g++.dg/other/i386-2.C: Ditto.
	* g++.dg/other/i386-3.C: Ditto.
	* gcc.target/i386/sse-22.c: Ditto.
	* gcc.target/i386/sse-23.c: Ditto.

From-SVN: r242569

re PR c++/55080 (-pedantic produces error: floating-point literal cannot appear in a constant-expression)

/cp
2016-11-17  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/55080
	* parser.c (cp_parser_non_integral_constant_expression): Issue a
	pedwarn instead of an error for case NIC_FLOAT.

/testsuite
2016-11-17  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/55080
	* g++.dg/parse/pr55080.C: New.

From-SVN: r242565

[gcc]
2016-11-17  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/78101
	* config/rs6000/predicates.md (fusion_addis_mem_combo_load): Add
	the appropriate checks for SFmode/DFmode load/stores in GPR
	registers.
	(fusion_addis_mem_combo_store): Likewise.
	* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Rename
	fusion_fpr_* to fusion_vsx_* and add in support for ISA 3.0 scalar
	d-form instructions for traditional Altivec registers.
	(emit_fusion_p9_load): Likewise.
	(emit_fusion_p9_store): Likewise.
	* config/rs6000/rs6000.md (p9 fusion store peephole2): Remove
	early clobber from scratch register.  Do not match if the register
	being stored is the scratch register.
	(fusion_vsx_<P:mode>_<FPR_FUSION:mode>_load): Rename fusion_fpr_*
	to fusion_vsx_* and add in support for ISA 3.0 scalar d-form
	instructions for traditional Altivec registers.
	(fusion_fpr_<P:mode>_<FPR_FUSION:mode>_load): Likewise.
	(fusion_vsx_<P:mode>_<FPR_FUSION:mode>_store): Likewise.
	(fusion_fpr_<P:mode>_<FPR_FUSION:mode>_store): Likewise.

[gcc/testsuite]
2016-11-17  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/78101
	* gcc.target/powerpc/fusion4.c: New test.

From-SVN: r242564

	* name-lookup.c (do_class_using_decl): Set CLASSTYPE_NON_AGGREGATE.

From-SVN: r242563

	* call.c (build_special_member_call): Handle CONSTRUCTOR.

From-SVN: r242562

	* parser.c (cp_parser_fold_expression): Check TREE_NO_WARNING.

From-SVN: r242561

2016-11-17  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    PR target/77933
    * config/arm/arm.c (thumb1_expand_prologue): Distinguish between lr
    being live in the function and lr needing to be saved.  Distinguish
    between already saved pushable registers and registers to push.
    Check for LR being an available pushable register.

    gcc/testsuite/
    PR target/77933
    * gcc.target/arm/pr77933-1.c: New test.
    * gcc.target/arm/pr77933-2.c: Likewise.

From-SVN: r242559