* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
	(AARCH64_ONLY, CHECK_CRYPTO): New macros.
	(Poly64x1_t, Poly64x2_t): Added types.
	* gcc.target/aarch64/advsimd-intrinsics/p64_p128.c
	(vmov_n_p64, vmovq_n_p64): Added.
	(vld2_lane_p64, vld2q_lane_p64): Likewise.
	(vld3_lane_p64, vld3q_lane_p64): Likewise.
	(vld4_lane_p64, vld4q_lane_p64): Likewise.
	(vst2_lane_p64, vst2q_lane_p64): Likewise.
	(vst3_lane_p64, vst3q_lane_p64): Likewise.
	(vst4_lane_p64, vst4q_lane_p64): Likewise.
	(vget_lane_p64, vgetq_lane_p64): Likewise.
	(vget_high_p64): Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c:
	Added AArch64 flags.
	(vreint_vector, vreint_vector_res): Moved to header.
	* gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c:
	Added Aarch64 flags.
	(vreint_vector, vreint_vector_res): Moved to header.

From-SVN: r242962

gcc/
2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>

        * config/arc/arc.c (arc_override_options): Avoid selection of
        compact casesi for ARCv2.

From-SVN: r242961

2016-11-29  Tobias Burnus  <burnus@net-b.de>

	PR fortran/58175
	* resolve.c (gfc_resolve_finalizers): Properly detect scalar finalizers.

2016-11-29  Janus Weil  <janus@gcc.gnu.org>

	PR fortran/58175
	* gfortran.dg/finalize_30.f90: New test case.

From-SVN: r242960

2016-11-29  Richard Biener  <rguenther@suse.de>

	* tree-cfg.c (lower_phi_internal_fn): Do not look for further
	PHIs after a regular stmt.
	(stmt_starts_bb_p): PHIs not preceeded by a PHI or a label
	start a new BB.

From-SVN: r242959

	PR gcov-profile/78582
	* gcc.dg/pr78582.c: New test.
	PR gcov-profile/78582
	* tree-profile.c (gimple_gen_time_profiler): Make one extra BB
	to prevent PHI argument clash.

From-SVN: r242958

The fix is now upstream.

	* LOCAL_PATCHES: Remove r242480.

From-SVN: r242957

gcc/
2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>

        * config/arc/arc.opt (marclinux): Fix typo.
        (marclinux_prof): Likewise.

From-SVN: r242956

gcc/
	* target.def (stack_protect_runtime_enabled_p): New.
	* function.c (expand_function_end): Guard stack_protect_epilogue with
	targetm.stack_protect_runtime_enabled_p.
	* cfgexpand.c (pass_expand::execute): Likewise.
	* calls.c (expand_call): Likewise.
	* doc/tm.texi.in (TARGET_STACK_PROTECT_RUNTIME_ENABLED_P): Add it.
	* doc/tm.texi: Regenerate.

From-SVN: r242955

The dump expects literals which would only be present if the target's
int size is 32 bits.

Fix by explicitly using 32 bit ints for targets with __SIZEOF_INT__ < 4.

gcc/testsuite/
2016-11-29  Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>

	* testsuite/gcc.dg/pr31096-1.c: Use __{U,}INT32_TYPE__ for
	targets with sizeof(int) < 4.

From-SVN: r242954

2016-11-29  Richard Biener  <rguenther@suse.de>

	PR middle-end/78546
	* match.pd: Add CST1 - (CST2 - A) -> CST3 + A missing case.

	* gcc.dg/tree-ssa/forwprop-36.c: New testcase.

From-SVN: r242953

2016-11-29  Janus Weil  <janus@gcc.gnu.org>

	* doc/contrib.texi: Add a few missing gfortran contributors.

From-SVN: r242952

These testcases test that we generate the expected code for all of the
rl*i* instructions, that is, rotate-and-mask and rotate-and-mask-insert
for immediate rotation counts.  All the testcases do rotate, shift left,
as well as shift right; if that results in an instruction that does not
exist the testcases generate a multiplication instead, so that we can
detect if this is handled properly.

Many 32-bit instructions zero-extend their result properly in 64-bit
mode, but the rs6000 port does not yet know.  These testcases test the
status quo, so they will need updating when ever we handle this.


gcc/testsuite/
	* gcc.target/powerpc/rldic-0.c: New testcase.
	* gcc.target/powerpc/rldic-1.c: New testcase.
	* gcc.target/powerpc/rldic-2.c: New testcase.
	* gcc.target/powerpc/rldicl-0.c: New testcase.
	* gcc.target/powerpc/rldicl-1.c: New testcase.
	* gcc.target/powerpc/rldicl-2.c: New testcase.
	* gcc.target/powerpc/rldicr-0.c: New testcase.
	* gcc.target/powerpc/rldicr-1.c: New testcase.
	* gcc.target/powerpc/rldicr-2.c: New testcase.
	* gcc.target/powerpc/rldicx.h: New file.
	* gcc.target/powerpc/rldimi-0.c: New testcase.
	* gcc.target/powerpc/rldimi-1.c: New testcase.
	* gcc.target/powerpc/rldimi-2.c: New testcase.
	* gcc.target/powerpc/rldimi.h: New file.
	* gcc.target/powerpc/rlwimi-0.c: New testcase.
	* gcc.target/powerpc/rlwimi-1.c: New testcase.
	* gcc.target/powerpc/rlwimi-2.c: New testcase.
	* gcc.target/powerpc/rlwimi.h: New file.
	* gcc.target/powerpc/rlwinm-0.c: New testcase.
	* gcc.target/powerpc/rlwinm-1.c: New testcase.
	* gcc.target/powerpc/rlwinm-2.c: New testcase.
	* gcc.target/powerpc/rlwinm.h: New file.

From-SVN: r242951

change_zero_ext handles (zero_extend:M1 (subreg:M2 (reg:M1) ...))
already; this patch extends it to also deal with any
(zero_extend:M1 (subreg:M2 (reg:M3) ...)) where the subreg is not
paradoxical.


	* combine.c (change_zero_ext): Also handle extends from a subreg
	to a mode bigger than that of the operand of the subreg.

From-SVN: r242950

If we use ABI_V4 and we have a big stack frame, we end the epilogue
with a "mr 1,11" (or similar) instruction.  This instruction however
has no dependencies on the earlier restores from stack (done via r11),
so sched2 can end up reordering the insns, which is bad because we
have no red zone so that you then restore from stack that is already
deallocated.

This fixes it by making that restore depend on the memory accesses.


	PR target/77687
	* config/rs6000/rs6000.c (rs6000_emit_stack_reset): Emit the
	stack_restore_tie insn instead of stack_tie, for the SVR4 and
	SPE ABIs.
	* config/rs6000/rs6000.md (stack_restore_tie): New define_insn.

From-SVN: r242949

This patch changes spread_components to use a simpler algorithm that
puts prologue components as early as possible, and epilogue components
as late as possible.  This allows better scheduling, and also saves a
bit of code size.  The blocks that run with some specific component
enabled after this patch is a strict superset of those that had it
before the patch.

It does this by finding for every component the basic blocks where that
component is not needed on some path from the entry block (it reuses
head_components to store this), and similarly the blocks where the
component is not needed on some path to the exit block (or the exit can
not be reached from that block) (stored in tail_components).  Blocks
that then are not in both of those two sets get the component active.


	* shrink-wrap.c (init_separate_shrink_wrap): Do not clear
	head_components and tail_components.
	(spread_components): New algorithm.
	(emit_common_tails_for_components): Clear head_components and
	tail_components.
	(insert_prologue_epilogue_for_components): Write extra output to the
	dump file for sibcalls and abnormal exits.

From-SVN: r242948

Combine can turn a conditional trap into an unconditional trap.  If it
does that it should make the code after it unreachable (an unconditional
trap should be the last insn in its bb, and that bb has no successors).

This patch seems to work.  It is hard to be sure, this is very hard to
trigger.  Quite a few other passes look like they need something similar
as well, but I don't see anything else handling it yet either.


	PR rtl-optimization/78342
	* combine.c: Include "cfghooks.h".
	(try_combine): If we create an unconditional trap, break the basic
	block in two just after it, and remove the edge between; also, set
	the *new_direct_jump_p flag so that cleanup_cfg is run.

From-SVN: r242947

simplify_truncation changes the truncation of many operations into
the operation on the truncation.  This patch makes this code also
handle extracts.


	* simplify-rtx.c (simplify_truncation): Handle truncate of zero_extract
	and sign_extract.

From-SVN: r242946

From-SVN: r242943

From-SVN: r242941

	* config/i386/i386.md (*and<mode>_1): Merge insn pattern from
	*andsi_1 and *andhi_1 using SWI24 mode iterator.  Use multi-line
	output template string.
	(*anddi_1): Use multi-line output template string.
	(*andqi_1): Ditto.

From-SVN: r242938

	PR middle-end/78540
	* rtl.h (remove_reg_equal_equiv_notes): Return bool instead of void.
	* rtlanal.c (remove_reg_equal_equiv_notes): Return true if any
	note has been removed.
	* postreload.c (reload_combine_recognize_pattern): If
	remove_reg_equal_equiv_notes returns true, call df_notes_rescan.

	* gcc.dg/pr78540.c: New test.

From-SVN: r242937

PR middle-end/78521 - [7 Regression] incorrect byte count in -Wformat-length warning with non-constant width or precision
PR middle-end/78520 - missing warning for snprintf with size greater than INT_MAX

gcc/ChangeLog:

	PR middle-end/78520
	* gimple-ssa-sprintf.c (target_max_value): Remove.
	(target_int_max, target_size_max): Use TYPE_MAX_VALUE.
	(get_width_and_precision): New function.
	(format_integer, format_floating, get_string_length, format_string):
	Correct handling of width and precision with unknown value.
	(format_directive): Add warning.
	(pass_sprintf_length::compute_format_length): Allow for precision
	to consist of a sole period with no asterisk or digits after it.

gcc/testsuite/ChangeLog:

	PR middle-end/78520
	* gcc.dg/tree-ssa/builtin-sprintf-5.c: Add test cases.
	* gcc.dg/tree-ssa/builtin-sprintf-6.c: New test.
	* gcc.dg/tree-ssa/builtin-sprintf-warn-1.c: Add test cases.
	* gcc.dg/tree-ssa/builtin-sprintf-warn-3.c: Add test cases.

From-SVN: r242935

	PR gcc/74748
	* libgcc/config/bfin/libgcc-glibc.ver, libgcc/config/bfin/t-linux:
	use generic linker version information on Blackfin.

2016-11-27  Iain Sandoe  <iain@codesourcery.com>

From-SVN: r242934

	PR gcc/74748
	* libgcc/mkmap-symver.awk: add support for skip_underscore

From-SVN: r242933

From-SVN: r242931

	PR c++/72808
	* decl.c (finish_enum_value_list): Call fixup_type_variants on
	current_class_type after
	insert_late_enum_def_into_classtype_sorted_fields.

	* g++.dg/debug/pr72808.C: New test.

Co-Authored-By: Jason Merrill <jason@redhat.com>

From-SVN: r242930

	PR rtl-optimization/78546
	* simplify-rtx.c (neg_const_int): When negating most negative
	number in mode wider than HOST_BITS_PER_WIDE_INT, use
	simplify_const_unary_operation to produce CONST_DOUBLE or
	CONST_WIDE_INT.
	(simplify_plus_minus): Hanlde the case where neg_const_int
	doesn't return a CONST_INT.

	* gcc.dg/torture/pr78546-1.c: New test.
	* gcc.dg/torture/pr78546-2.c: New test.

From-SVN: r242929

Running bootstrap-ubsan on ppc64le shows many instances of e.g.:
 config/rs6000/rs6000.c:6217:36: runtime error: left shift of negative value -12301

        PR target/78556
	* config/rs6000/rs6000.c (vspltis_constant): Add casts to avoid
	left shifting of negative values.

From-SVN: r242928

	PR fortran/78298
	* tree-nested.c (convert_local_reference_stmt): After adding
	shared (FRAME.NN) clause to omp parallel, task or target,
	add it also to all outer omp parallel, task or target constructs.

	* gfortran.dg/gomp/pr78298.f90: New test.

From-SVN: r242926

	* config/i386/i386.md (UNSPEC_KMASKOP): New.
	(UNSPEC_KMOV): Remove.
	(kmovw): Expand to plain HImode move.
	(k<any_logic:code><mode>): Rename from *k<logic><mode>. Use
	register_operand predicates.  Tag pattern with UNSPEC_KMASKOP.
	Remove corresponding clobber-removing splitter.
	(*anddi_1): Remove mask register alternatives.
	(*andsi_1): Ditto.
	(*andhi_1): Ditto.
	(*andqi_1): Ditto.
	(*<any_or:code><mode>_1): Ditto.
	(*<any_or:code>qi_1): Ditto.
	(kandn<mode>): Use SWI1248_AVX512BW mode iterator.  Remove
	general register alternatives.  Tag pattern with UNSPEC_KMASKOP.
	Remove corresponding splitter to operation with general registers.
	(*andn<SWI38:mode>): Rename from *bmi_andn_<mode>.
	(*andn<SWI12:mode>): New pattern.
	(*kxnor<mode>): Remove general register alternatives.  Tag pattern
	with UNSPEC_KMASKOP.  Remove corresponding splitter to operation
	with general registers.
	(knot<mode>): New insn pattern.
	(*one_cmpl<mode>2_1): Remove mask register alternatives.
	(one_cmplqi2_1): Ditto.
	(*k<any_lshift:code><mode>): Rename from *k<mshift><mode>3.
	Tag pattern with UNSPEC_KMASKOP. Add mode attribute.
	* config/i386/predicates.md (mask_reg_operand): Remove predicate.
	* config/i386/sse.md (vec_unpacks_hi_hi): Update pattern
	to generate kmaskop shift.
	(vec_unpacks_hi_<mode>): Ditto.
	* config/i386/i386-builtin.def (__builtin_ia32_kandhi):
	Use CODE_FOR_kandhi.
	(__builtin_ia32_knothi): Use CODE_FOR_knothi.
	(__builtin_ia32_korhi): Use CODE_FOR_kiorhi.
	(__builtin_ia32_kxorhi): Use CODE_FOR_kxorhi.

testsuite/ChangeLog:

	* gcc.target/i386/bmi-andn-1a.c (dg-final): Update scan string.
	* gcc.target/i386/bmi-andn-2a.c (dg-final): Ditto.

From-SVN: r242925

re PR c++/77591 (decltype(auto) and ternary operator allow returning local reference without a warning)

	PR c++/77591
	* typeck.c (maybe_warn_about_returning_address_of_local): Optimize
	whats_returned through fold_for_warn.

	* g++.dg/cpp1y/pr77591.C: New test.

From-SVN: r242924

From-SVN: r242923

From-SVN: r242922

tree-vrp.c (vrp_visit_assignment_or_call): Handle simplifications to SSA names via extract_range_from_ssa_name if allowed.

2016-11-28  Richard Biener  <rguenther@suse.de>

	* tree-vrp.c (vrp_visit_assignment_or_call): Handle
	simplifications to SSA names via extract_range_from_ssa_name
	if allowed.

From-SVN: r242921

2016-11-28  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/78542
	* tree-ssa-ccp.c (evaluate_stmt): Only valueize simplification
	if allowed.

	* gcc.dg/torture/pr78542.c: New testcase.

From-SVN: r242920

	* config/nvptx/critical.c: Delete to use generic implementation.

From-SVN: r242919

2016-11-28  Jonas Hahnfeld  <Hahnfeld@itc.rwth-aachen.de>

	* config/linux/affinity.c [!HAVE_PTHREAD_AFFINITY_NP]: Include
	../../affinity.c as fallback.
	* config/nvptx/affinity.c: Delete to use fallback implementation.

From-SVN: r242918

gcc:
* combine.c (simplify_if_then_else): Simplify IF_THEN_ELSE
that isolates a single bit, even if the condition involves
subregs.

From-SVN: r242917

	* config/aarch64/aarch64-simd-builtins.def
	(BSL_P): Added di and v2di mode.
	* config/aarch64/arm_neon.h
	(vsriq_n_p64, vsri_n_p64): Added poly type.
	(vextq_p64, vext_p64): Likewise.
	(vceq_p64, vbslq_p64, vbsl_p64): Likewise.

From-SVN: r242916

2016-11-28  Tamar Christina  <tamar.christina@arm.com>

	* config/aarch64/aarch64-builtins.c (TYPES_SETREGP): Added poly type.
	(TYPES_GETREGP): Likewise.
	(TYPES_SHIFTINSERTP): Likewise.
	(TYPES_COMBINEP): Likewise.
	(TYPES_STORE1P): Likewise.
	* config/aarch64/aarch64-simd-builtins.def
	(combine): Added poly generator.
	(get_dregoi): Likewise.
	(get_dregci): Likewise.
	(get_dregxi): Likewise.
	(ssli_n): Likewise.
	(ld1): Likewise.
	(st1): Likewise.
	* config/aarch64/arm_neon.h
	(poly64x1x2_t, poly64x1x3_t): New.
	(poly64x1x4_t, poly64x2x2_t): Likewise.
	(poly64x2x3_t, poly64x2x4_t): Likewise.
	(poly64x1_t): Likewise.
	(vcreate_p64, vcombine_p64): Likewise.
	(vdup_n_p64, vdupq_n_p64): Likewise.
	(vld2_p64, vld2q_p64): Likewise.
	(vld3_p64, vld3q_p64): Likewise.
	(vld4_p64, vld4q_p64): Likewise.
	(vld2_dup_p64, vld3_dup_p64): Likewise.
	(vld4_dup_p64, vsli_n_p64): Likewise.
	(vsliq_n_p64, vst1_p64): Likewise.
	(vst1q_p64, vst2_p64): Likewise.
	(vst3_p64, vst4_p64): Likewise.
	(__aarch64_vdup_lane_p64, __aarch64_vdup_laneq_p64): Likewise.
	(__aarch64_vdupq_lane_p64, __aarch64_vdupq_laneq_p64): Likewise.
	(vget_lane_p64, vgetq_lane_p64): Likewise.
	(vreinterpret_p8_p64, vreinterpretq_p8_p64): Likewise.
	(vreinterpret_p16_p64, vreinterpretq_p16_p64): Likewise.
	(vreinterpret_p64_f16, vreinterpret_p64_f64): Likewise.
	(vreinterpret_p64_s8, vreinterpret_p64_s16): Likewise.
	(vreinterpret_p64_s32, vreinterpret_p64_s64): Likewise.
	(vreinterpret_p64_f32, vreinterpret_p64_u8): Likewise.
	(vreinterpret_p64_u16, vreinterpret_p64_u32): Likewise.
	(vreinterpret_p64_u64, vreinterpret_p64_p8): Likewise.
	(vreinterpretq_p64_f64, vreinterpretq_p64_s8): Likewise.
	(vreinterpretq_p64_s16, vreinterpretq_p64_s32): Likewise.
	(vreinterpretq_p64_s64, vreinterpretq_p64_f16): Likewise.
	(vreinterpretq_p64_f32, vreinterpretq_p64_u8): Likewise.
	(vreinterpretq_p64_u16, vreinterpretq_p64_u32): Likewise.
	(vreinterpretq_p64_u64, vreinterpretq_p64_p8): Likewise.
	(vreinterpret_f16_p64, vreinterpretq_f16_p64): Likewise.
	(vreinterpret_f32_p64, vreinterpretq_f32_p64): Likewise.
	(vreinterpret_f64_p64, vreinterpretq_f64_p64): Likewise.
	(vreinterpret_s64_p64, vreinterpretq_s64_p64): Likewise.
	(vreinterpret_u64_p64, vreinterpretq_u64_p64): Likewise.
	(vreinterpret_s8_p64, vreinterpretq_s8_p64): Likewise.
	(vreinterpret_s16_p64, vreinterpret_s32_p64): Likewise.
	(vreinterpretq_s32_p64, vreinterpret_u8_p64): Likewise.
	(vreinterpret_u16_p64, vreinterpretq_u16_p64): Likewise.
	(vreinterpret_u32_p64, vreinterpretq_u32_p64): Likewise.
	(vset_lane_p64, vsetq_lane_p64): Likewise.
	(vget_low_p64, vget_high_p64): Likewise.
	(vcombine_p64, vst2_lane_p64): Likewise.
	(vst3_lane_p64, vst4_lane_p64): Likewise.
	(vst2q_lane_p64, vst3q_lane_p64): Likewise.
	(vst4q_lane_p64, vget_lane_p64): Likewise.
	(vget_laneq_p64, vset_lane_p64): Likewise.
	(vset_laneq_p64, vcopy_lane_p64): Likewise.
	(vcopy_laneq_p64, vdup_n_p64): Likewise.
	(vdupq_n_p64, vdup_lane_p64): Likewise.
	(vdup_laneq_p64, vld1_p64): Likewise.
	(vld1q_p64, vld1_dup_p64): Likewise.
	(vld1q_dup_p64, vld1q_dup_p64): Likewise.
	(vmov_n_p64, vmovq_n_p64): Likewise.
	(vst3q_p64, vst4q_p64): Likewise.
	(vld1_lane_p64, vld1q_lane_p64): Likewise.
	(vst1_lane_p64, vst1q_lane_p64): Likewise.
	(vcopy_laneq_p64, vcopyq_laneq_p64): Likewise.
	(vdupq_laneq_p64): Likewise.

From-SVN: r242915