This option is not useful on its own as all posix modules require the
compiler to predefine version(Posix) anyway.  So the option has been
removed, and logic moved into DRUNTIME_OS_SOURCES, where the conditional
DRUNTIME_OS_POSIX is set instead.

libphobos/ChangeLog:

	* configure: Regenerate.
	* configure.ac: Remove DRUNTIME_OS_UNIX.
	* libdruntime/Makefile.am: Add DRUNTIME_DSOURCES_POSIX if
	DRUNTIME_OS_POSIX is true.
	* libdruntime/Makefile.in: Regenerate.
	* m4/druntime/os.m4 (DRUNTIME_OS_UNIX): Remove, move AM_CONDITIONAL
	logic to...
	(DRUNTIME_OS_SOURCES): ...here.  Rename conditional to
	DRUNTIME_OS_POSIX.

The following testcase ICEs on m68k (and another one Jeff mailed me
privately on microblaze).
The problem is that reload creates two DEBUG_INSNs with the same
value of (plus:P (reg:P sp) (const_int 0)), we compute correctly the
same hash value for them, but then don't find them in the cselib hash table,
as rtx_equal_for_cselib_1 thinks it is different from (reg:P sp),
and trigger an assertion failure that requires that from two different debug
insns one doesn't add locations to VALUEs.

The patch has two fixes for this, each fixes the ICE on both targets
separately, but I think we want both.

The cselib.c change ensures that rtx_equal_for_cselib_1 considers
(value:P sp_derived_value) and (plus:P (reg:P sp) (const_int 0)) equivalent.

The reload1.c change makes sure we don't create those bogus plus 0
expressions.  I understand the reasons for creating them, but they don't
really apply to DEBUG_INSNs; we don't have validity matching there, all we
care is that the expressions aren't arbitrarily deep, but it is just fine
to fold x + 0 into just x in there.

2020-04-08  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/94526
	* cselib.c (autoinc_split): Handle e->val_rtx being SP_DERIVED_VALUE_P
	with zero offset.
	* reload1.c (eliminate_regs_1): Avoid creating
	(plus (reg) (const_int 0)) in DEBUG_INSNs.

	* gcc.dg/pr94526.c: New test.

The first testcase below is miscompiled, because for the division part
of the lowering we canonicalize negative divisors to their absolute value
(similarly how expmed.c canonicalizes it), but when multiplying the division
result back by the VECTOR_CST, we use the original constant, which can
contain negative divisors.

Fixed by computing ABS_EXPR of the VECTOR_CST.  Unfortunately, fold-const.c
doesn't support const_unop (ABS_EXPR, VECTOR_CST) and I think it is too late
in GCC 10 cycle to add it now.

Furthermore, while modulo by most negative constant happens to return the
right value, it does that only by invoking UB in the IL, because
we then expand division by that 1U+INT_MAX and say for INT_MIN % INT_MIN
compute the division as -1, and then multiply by INT_MIN, which is signed
integer overflow.  We in theory could do the computation in unsigned vector
types instead, but is it worth bothering.  People that are doing % INT_MIN
are either testing for standard conformance, or doing something wrong.
So, I've also added punting on % INT_MIN, both in vect lowering and vect
pattern recognition (we punt already for / INT_MIN).

2020-04-08  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/94524
	* tree-vect-generic.c (expand_vector_divmod): If any elt of op1 is
	negative for signed TRUNC_MOD_EXPR, multiply with absolute value of
	op1 rather than op1 itself at the end.  Punt for signed modulo by
	most negative constant.
	* tree-vect-patterns.c (vect_recog_divmod_pattern): Punt for signed
	modulo by most negative constant.

	* gcc.c-torture/execute/pr94524-1.c: New test.
	* gcc.c-torture/execute/pr94524-2.c: New test.

The test FAIL everywhere where size_t is not unsigned long.  Fixed by
using __SIZE_TYPE__ instead.

2020-04-08  Jakub Jelinek  <jakub@redhat.com>

	PR c++/94314
	* g++.dg/pr94314.C (A::operator new, B::operator new, C::operator new):
	Use __SIZE_TYPE__ instead of unsigned long.
	* g++.dg/pr94314-3.C (base::operator new, B::operator new): Likewise.

This test has been put in a wrong directory, where OpenACC tests aren't
tested with -fopenacc, and also contained trailing semicolons.
I've moved it where it belongs, added dg-error directives and removed
the extra semicolons.

2020-04-08  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/94120
	PR testsuite/94533
	* g++.dg/declare-pr94120.C: Move test to ...
	* g++.dg/goacc/declare-pr94120.C: ... here.  Add dg-error directives.

While reducing something else I noticed that we ICE on the following
invalid code.  In tsubst_lambda_expr, tsubst_template_decl has already
reported an error and returned the error_mark_node, so make sure we
don't ICE on that.  I'm using a goto here because we still have to
do finish_struct because it does popclass ().

	PR c++/94507 - ICE-on-invalid with lambda template.
	* pt.c (tsubst_lambda_expr): Cope when tsubst_template_decl or
	tsubst_function_decl returns error_mark_node.

	* g++.dg/cpp2a/lambda-generic7.C: New test.

It turns out RTL CSE tries to remove redundant stores but fails to
do the usual validity check what such a change is TBAA neutral to
later loads.

This now triggers with the PR93946 testcases on nios2.

2020-04-08  Richard Biener  <rguenther@suse.de>

	PR rtl-optimization/93946
	* cse.c (cse_insn): Record the tabled expression in
	src_related.  Verify a redundant store removal is valid.

dg-require-effective-target arm_fp16_alternative_ok may pass even when
arm_fp16_ok doesn't, and the latter's failure inhibits dg-add-options
arm_fp16_alternative.  Requiring arm_fp16_ok would disable the test,
but if we just pass it the -mfp16-format=alternative option, it passes
even without arm_fp16_ok.  Sibling test fp16-aapcs-4.c underwent a
similar change, so I'm proposing the explicit option to fp16-aapcs-3.c
as well.


for  gcc/testsuite/ChangeLog

	* gcc.target/arm/fp16-aapcs-3.c: Explicitly use the
	-mfp16-format=alternative option.

Since constant_call_address_operand has

;; Test for a pc-relative call operand
(define_predicate "constant_call_address_operand"
  (match_code "symbol_ref")
{
  if (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC
      || flag_force_indirect_call)
    return false;
  if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
    return false;
  return true;
})

even if cgraph_node::get (cfun->decl)->only_called_directly_p () returns
false, the fuction may still be called indirectly.  Copy the logic from
constant_call_address_operand to rest_of_insert_endbranch to insert ENDBR
at function entry if function will be called indirectly.

gcc/

	PR target/94417
	* config/i386/i386-features.c (rest_of_insert_endbranch): Insert
	ENDBR at function entry if function will be called indirectly.

gcc/testsuite/

	PR target/94417
	* gcc.target/i386/pr94417-1.c: New test.
	* gcc.target/i386/pr94417-2.c: Likewise.
	* gcc.target/i386/pr94417-3.c: Likewise.

The ix86_get_mask_mode hook uses int mask for 512-bit vectors or 128/256-bit
vectors with AVX512VL (that is correct), and only for V*[SD][IF]mode if not
AVX512BW (also correct), but with AVX512BW it would stop checking the
elem_size altogether and pretend the hw has masking support for V*TImode
etc., which it doesn't.  That can lead to various ICEs later on.

2020-04-08  Jakub Jelinek  <jakub@redhat.com>

	PR target/94438
	* config/i386/i386.c (ix86_get_mask_mode): Only use int mask for elem_size
	1, 2, 4 and 8.

	* gcc.target/i386/avx512bw-pr94438.c: New test.
	* gcc.target/i386/avx512vlbw-pr94438.c: New test.

	PR fortran/93871
	* gfortran.dg/dec_math_5.f90: Move to ...
	* gfortran.dg/ieee/dec_math_1.f90: ... here; change
	dg-options to dg-additional-options.

Some more C++20 changes from P1614R2, "The Mothership has Landed".

	* include/bits/slice_array.h (operator==(const slice&, const slice&)):
	Define for C++20.
	* include/std/complex (operator==(const T&, const complex<T>&))
	(operator!=(const complex<T>&, const complex<T>&))
	(operator!=(const complex<T>&, const T&))
	(operator!=(const T&, const complex<T>&)): Do not declare for C++20.
	* testsuite/26_numerics/slice/compare.cc: New test.

All TLS execution tests require tls_runtime, not just tls; pr78796.c
is the only exception that is not otherwise limited to platforms known
to support it.  I suppose that's an oversight.  On a platform whose
linker is configured to disregard TLS relocations, this test compiles
and assembles successfully, but execution fails.  The tls_runtime
requirement target avoids the noise from the expected failure.


for  gcc/testsuite/ChangeLog

	* gcc.dg/tls/pr78796.c: Require tls_runtime.

	PR c++/94314
	* gimple.c (gimple_call_operator_delete_p): Rename to...
	(gimple_call_replaceable_operator_delete_p): ... this.
	Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P.
	* gimple.h (gimple_call_operator_delete_p): Rename to ...
	(gimple_call_replaceable_operator_delete_p): ... this.
	* tree-core.h (tree_function_decl): Add replaceable_operator
	flag.
	* tree-ssa-dce.c (mark_all_reaching_defs_necessary_1):
	Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P.
	(propagate_necessity): Use gimple_call_replaceable_operator_delete_p.
	(eliminate_unnecessary_stmts): Likewise.
	* tree-streamer-in.c (unpack_ts_function_decl_value_fields):
	Pack DECL_IS_REPLACEABLE_OPERATOR.
	* tree-streamer-out.c (pack_ts_function_decl_value_fields):
	Unpack the field here.
	* tree.h (DECL_IS_REPLACEABLE_OPERATOR): New.
	(DECL_IS_REPLACEABLE_OPERATOR_NEW_P): New.
	(DECL_IS_REPLACEABLE_OPERATOR_DELETE_P): New.
	* cgraph.c (cgraph_node::dump): Dump if an operator is replaceable.
	* ipa-icf.c (sem_item::compare_referenced_symbol_properties): Compare
	replaceable operator flags.
	PR c++/94314
	* decl.c (duplicate_decls): Duplicate also DECL_IS_REPLACEABLE_OPERATOR.
	(cxx_init_decl_processing): Mark replaceable all implicitly defined
	operators.
	PR c++/94314
	* lto-common.c (compare_tree_sccs_1): Compare also
	DECL_IS_REPLACEABLE_OPERATOR.
	PR c++/94314
	* g++.dg/pr94314-2.C: New test.
	* g++.dg/pr94314-3.C: New test.
	* g++.dg/pr94314.C: New test.

Some more C++20 changes from P1614R2, "The Mothership has Landed".

	* include/std/charconv (to_chars_result, from_chars_result): Add
	defaulted equality comparisons for C++20.
	* testsuite/20_util/from_chars/compare.cc: New test.
	* testsuite/20_util/to_chars/compare.cc: New test.

These intrinsics are the predicated version of the intrinsics inroduced
in https://gcc.gnu.org/pipermail/gcc-patches/2020-March/542725.html.

These are not yet public on developer.arm.com but we have reached
internal consensus on them.

The approach follows the same method as for the CDE intrinsics for MVE
registers, most notably using the same arm_resolve_overloaded_builtin
function with minor modifications.

The resolver hook has been moved from arm-builtins.c to arm-c.c so it
can access the c-common function build_function_call_vec.  This function
is needed to perform the same checks on arguments as a normal C or C++
function would perform.
It is fine to put this resolver in arm-c.c since it's only use is for
the ACLE functions, and these are only available in C/C++.
So that the resolver function has access to information it needs from
the builtins, we put two query functions into arm-builtins.c and use
them from arm-c.c.

We rely on the order that the builtins are defined in
gcc/config/arm/arm_cde_builtins.def, knowing that the predicated
versions come after the non-predicated versions.

The machine description patterns for these builtins are simpler than
those for the non-predicated versions, since the accumulator versions
*and* non-accumulator versions both need an input vector now.
The input vector is needed for the non-accumulator version to describe
the original values for those lanes that are not updated during the
merge operation.

We additionally need to introduce qualifiers for these new builtins,
which follow the same pattern as the non-predicated versions but with an
extra argument to describe the predicate.

Error message changes:
- We directly mention the builtin argument when complaining that an
  argument is not in the correct range.
  This more closely matches the C error messages.
- We ensure the resolver complains about *all* invalid arguments to a
  function instead of just the first one.
- The resolver error messages index arguments from 1 instead of 0 to
  match the arguments coming from the C/C++ frontend.

In order to allow the user to give an argument for the merging predicate
when they don't care what data is stored in the 'false' lanes, we also
move the __arm_vuninitializedq* intrinsics from arm_mve.h to
arm_mve_types.h which is shared with arm_cde.h.

We only move the fully type-specified `__arm_vuninitializedq*`
intrinsics and not the polymorphic versions, since moving the
polymorphic versions requires moving the _Generic framework as well as
just the intrinsics we're interested in.  This matches the approach taken
for the `__arm_vreinterpret*` functions in this include file.

This patch also contains a slight change in spacing of an existing
assembly instruction to be emitted.
This is just to help writing tests -- vmsr usually has a tab and a space
between the mnemonic and the first argument, but in one case it just has
a tab -- making all the same helps make test regexps simpler.

Testing Done:
    Bootstrap and full regtest on arm-none-linux-gnueabihf
    Full regtest on arm-none-eabi

    All testing done with a local fix for the bugzilla PR below.
    That bugzilla currently causes multiple ICE's on the tests added in
    this patch.
    https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94341

gcc/ChangeLog:

2020-04-02  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/arm/arm-builtins.c (CX_UNARY_UNONE_QUALIFIERS): New.
	(CX_BINARY_UNONE_QUALIFIERS): New.
	(CX_TERNARY_UNONE_QUALIFIERS): New.
	(arm_resolve_overloaded_builtin): Move to arm-c.c.
	(arm_expand_builtin_args): Update error message.
	(enum resolver_ident): New.
	(arm_describe_resolver): New.
	(arm_cde_end_args): New.
	* config/arm/arm-builtins.h: New file.
	* config/arm/arm-c.c (arm_resolve_overloaded_builtin): New.
	(arm_resolve_cde_builtin): Moved from arm-builtins.c.
	* config/arm/arm_cde.h (__arm_vcx1q_m, __arm_vcx1qa_m,
	__arm_vcx2q_m, __arm_vcx2qa_m, __arm_vcx3q_m, __arm_vcx3qa_m):
	New.
	* config/arm/arm_cde_builtins.def (vcx1q_p_, vcx1qa_p_,
	vcx2q_p_, vcx2qa_p_, vcx3q_p_, vcx3qa_p_): New builtin defs.
	* config/arm/iterators.md (CDE_VCX): New int iterator.
	(a) New int attribute.
	* config/arm/mve.md (arm_vcx1q<a>_p_v16qi, arm_vcx2q<a>_p_v16qi,
	arm_vcx3q<a>_p_v16qi): New patterns.
	* config/arm/vfp.md (thumb2_movhi_fp16): Extra space in assembly.

gcc/testsuite/ChangeLog:

2020-04-02  Matthew Malcomson  <matthew.malcomson@arm.com>

	* gcc.target/arm/acle/cde-errors.c: Add predicated forms.
	* gcc.target/arm/acle/cde-mve-error-1.c: Add predicated forms.
	* gcc.target/arm/acle/cde-mve-error-2.c: Add predicated forms.
	* gcc.target/arm/acle/cde-mve-error-3.c: Add predicated forms.
	* gcc.target/arm/acle/cde-mve-full-assembly.c: Add predicated
	forms.
	* gcc.target/arm/acle/cde-mve-tests.c: Add predicated forms.
	* gcc.target/arm/acle/cde_v_1_err.c (test_imm_range): Update for
	error message format change.
	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c:
	Update scan-assembler regexp.

Implement CDE intrinsics on MVE registers.

Other than the basics required for adding intrinsics this patch consists
of three changes.

** We separate out the MVE types and casts from the arm_mve.h header.

This is so that the types can be used in arm_cde.h without the need to include
the entire arm_mve.h header.
The only type that arm_cde.h needs is `uint8x16_t`, so this separation could be
avoided by using a `typedef` in this file.
Since the introduced intrinsics are all defined to act on the full range of MVE
types, declaring all such types seems intuitive since it will provide their
declaration to the user too.

This arm_mve_types.h header not only includes the MVE types, but also
the conversion intrinsics between them.
Some of the conversion intrinsics are needed for arm_cde.h, but most are
not.  We include all conversion intrinsics to keep the definition of
such conversion functions all in one place, on the understanding that
extra conversion functions being defined when including `arm_cde.h` is
not a problem.

** We define the TARGET_RESOLVE_OVERLOADED_BUILTIN hook for the Arm backend.

This is needed to implement the polymorphism for the required intrinsics.
The intrinsics have no specialised version, and the resulting assembly
instruction for all different types should be exactly the same.
Due to this we have implemented these intrinsics via one builtin on one type.
All other calls to the intrinsic with different types are implicitly cast to
the one type that is defined, and hence are all expanded to the same RTL
pattern that is only defined for one machine mode.

** We seperate the initialisation of the CDE intrinsics from others.

This allows us to ensure that the CDE intrinsics acting on MVE registers
are only created when both CDE and MVE are available.
Only initialising these builtins when both features are available is
especially important since they require a type that is only initialised
when the target supports hard float.  Hence trying to initialise these
builtins on a soft float target would cause an ICE.

Testing done:
  Full bootstrap and regtest on arm-none-linux-gnueabihf
  Regression test on arm-none-eabi

Ok for trunk?

gcc/ChangeLog:

2020-03-10  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config.gcc (arm_mve_types.h): New extra_header for arm.
	* config/arm/arm-builtins.c (arm_resolve_overloaded_builtin): New.
	(arm_init_cde_builtins): New.
	(arm_init_acle_builtins): Remove initialisation of CDE builtins.
	(arm_init_builtins): Call arm_init_cde_builtins when target
	supports CDE.
	* config/arm/arm-c.c (arm_resolve_overloaded_builtin): New declaration.
	(arm_register_target_pragmas): Initialise resolve_overloaded_builtin
	hook to the implementation for the arm backend.
	* config/arm/arm.h (ARM_MVE_CDE_CONST_1): New.
	(ARM_MVE_CDE_CONST_2): New.
	(ARM_MVE_CDE_CONST_3): New.
	* config/arm/arm_cde.h (__arm_vcx1q_u8): New.
	(__arm_vcx1qa): New.
	(__arm_vcx2q): New.
	(__arm_vcx2q_u8): New.
	(__arm_vcx2qa): New.
	(__arm_vcx3q): New.
	(__arm_vcx3q_u8): New.
	(__arm_vcx3qa): New.
	* config/arm/arm_cde_builtins.def (vcx1q, vcx1qa, vcx2q, vcx2qa, vcx3q,
	vcx3qa): New builtins defined.
	* config/arm/arm_mve.h: Move typedefs and conversion intrinsics
	to arm_mve_types.h header.
	* config/arm/arm_mve_types.h: New file.
	* config/arm/mve.md (arm_vcx1qv16qi, arm_vcx1qav16qi, arm_vcx2qv16qi,
	arm_vcx2qav16qi, arm_vcx3qv16qi, arm_vcx3qav16qi): New patterns.
	* config/arm/predicates.md (const_int_mve_cde1_operand,
	const_int_mve_cde2_operand, const_int_mve_cde3_operand): New.

gcc/testsuite/ChangeLog:

2020-03-23  Matthew Malcomson  <matthew.malcomson@arm.com>
	    Dennis Zhang  <dennis.zhang@arm.com>

	* gcc.target/arm/acle/cde-mve-error-1.c: New test.
	* gcc.target/arm/acle/cde-mve-error-2.c: New test.
	* gcc.target/arm/acle/cde-mve-error-3.c: New test.
	* gcc.target/arm/acle/cde-mve-full-assembly.c: New test.
	* gcc.target/arm/acle/cde-mve-tests.c: New test.
	* lib/target-supports.exp (arm_v8_1m_main_cde_mve_fp): New check
	effective.
	(arm_v8_1m_main_cde_mve, arm_v8m_main_cde_fp): Use -mfpu=auto
	so we only check configurations that make sense.

This patch introduces the scalar CDE (Custom Datapath Extension)
intrinsics for the arm backend.

There is nothing beyond the standard in this patch.  We simply build upon what
has been done by Dennis for the vector intrinsics.

We do add `+cdecp6` to the default arguments for `target-supports.exp`, this
allows for using coprocessor 6 in tests. This patch uses an alternate
coprocessor to ease assembler scanning by looking for a use of coprocessor 6.

We also ensure that any DImode registers are put in an even-odd register pair
when compiling for a target with CDE -- this avoids faulty code generation for
-Os when producing the cx*d instructions.

Testing done:
Bootstrapped and regtested for arm-none-linux-gnueabihf.

gcc/ChangeLog:

2020-03-03  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/arm/arm.c (arm_hard_regno_mode_ok): DImode registers forced
	into even-odd register pairs for TARGET_CDE.
	* config/arm/arm.h (ARM_CCDE_CONST_1): New.
	(ARM_CCDE_CONST_2): New.
	(ARM_CCDE_CONST_3): New.
	* config/arm/arm.md (arm_cx1si, arm_cx1di arm_cx1asi, arm_cx1adi,
	arm_cx2si, arm_cx2di arm_cx2asi, arm_cx2adi arm_cx3si, arm_cx3di,
	arm_cx3asi, arm_cx3adi): New patterns.
	* config/arm/arm_cde.h (__arm_cx1, __arm_cx1a, __arm_cx2, __arm_cx2a,
	__arm_cx3, __arm_cx3a, __arm_cx1d, __arm_cx1da, __arm_cx2d, __arm_cx2da,
	__arm_cx3d, __arm_cx3da): New ACLE function macros.
	* config/arm/arm_cde_builtins.def (cx1, cx1a, cx2, cx2a, cx3, cx3a):
	Define intrinsics.
	* config/arm/iterators.md (cde_suffix, cde_dest): New mode attributes.
	* config/arm/predicates.md (const_int_ccde1_operand,
	const_int_ccde2_operand, const_int_ccde3_operand): New.
	* config/arm/unspecs.md (UNSPEC_CDE, UNSPEC_CDEA): New.

gcc/testsuite/ChangeLog:

2020-03-03  Matthew Malcomson  <matthew.malcomson@arm.com>

	* gcc.target/arm/acle/cde-errors.c: New test.
	* gcc.target/arm/acle/cde.c: New test.
	* lib/target-supports.exp: Update CDE flags to enable coprocessor 6.

This patch enables the ACLE intrinsics calling VCX1<A>,
VCX2<A>, and VCX3<A> instructions who work with FPU/MVE
32-bit/64-bit registers. This patch also enables DImode for VFP
to support CDE with FPU.

gcc/ChangeLog:
2020-04-08  Dennis Zhang  <dennis.zhang@arm.com>
	    Matthew Malcomson <matthew.malcomson@arm.com>

	* config/arm/arm-builtins.c (CX_IMM_QUALIFIERS): New macro.
	(CX_UNARY_QUALIFIERS, CX_BINARY_QUALIFIERS): Likewise.
	(CX_TERNARY_QUALIFIERS): Likewise.
	(ARM_BUILTIN_CDE_PATTERN_START): Likewise.
	(ARM_BUILTIN_CDE_PATTERN_END): Likewise.
	(arm_init_acle_builtins): Initialize CDE builtins.
	(arm_expand_acle_builtin): Check CDE constant operands.
	* config/arm/arm.h (ARM_CDE_CONST_COPROC): New macro to set the range
	of CDE constant operand.
	* config/arm/arm.c (arm_hard_regno_mode_ok): Support DImode for
	TARGET_VFP_BASE.
	(ARM_VCDE_CONST_1, ARM_VCDE_CONST_2, ARM_VCDE_CONST_3): Likewise.
	* config/arm/arm_cde.h (__arm_vcx1_u32): New macro of ACLE interface.
	(__arm_vcx1a_u32, __arm_vcx2_u32, __arm_vcx2a_u32): Likewise.
	(__arm_vcx3_u32, __arm_vcx3a_u32, __arm_vcx1d_u64): Likewise.
	(__arm_vcx1da_u64, __arm_vcx2d_u64, __arm_vcx2da_u64): Likewise.
	(__arm_vcx3d_u64, __arm_vcx3da_u64): Likewise.
	* config/arm/arm_cde_builtins.def: New file.
	* config/arm/iterators.md (V_reg): New attribute of SI.
	* config/arm/predicates.md (const_int_coproc_operand): New.
	(const_int_vcde1_operand, const_int_vcde2_operand): New.
	(const_int_vcde3_operand): New.
	* config/arm/unspecs.md (UNSPEC_VCDE, UNSPEC_VCDEA): New.
	* config/arm/vfp.md (arm_vcx1<mode>): New entry.
	(arm_vcx1a<mode>, arm_vcx2<mode>, arm_vcx2a<mode>): Likewise.
	(arm_vcx3<mode>, arm_vcx3a<mode>): Likewise.

gcc/testsuite/ChangeLog:
2020-04-08  Dennis Zhang  <dennis.zhang@arm.com>

	* gcc.target/arm/acle/cde_v_1.c: New test.
	* gcc.target/arm/acle/cde_v_1_err.c: New test.
	* gcc.target/arm/acle/cde_v_1_mve.c: New test.

This resolves parts of Core issues 1001/1322 by rebuilding the function type
of an instantiated function template in terms of its formal parameter types
whenever the original function type and formal parameter types disagree about
the type of a parameter after substitution.

gcc/cp/ChangeLog:

	Core issues 1001 and 1322
	PR c++/92010
	* pt.c (rebuild_function_or_method_type): Split function out from ...
	(tsubst_function_type): ... here.
	(maybe_rebuild_function_decl_type): New function.
	(tsubst_function_decl): Use it.

gcc/testsuite/ChangeLog:

	Core issues 1001 and 1322
	PR c++/92010
	* g++.dg/cpp2a/lambda-uneval11.c: New test.
	* g++.dg/template/array33.C: New test.
	* g++.dg/template/array34.C: New test.
	* g++.dg/template/defarg22.C: New test.

This patch is part of a series that adds support for the Arm Custom
Datapath Extension. It defines the options cdecp0-cdecp7 for CLI to
enable the CDE on corresponding coprocessor 0-7.
It also adds new target supports for CDE feature testsuite.

gcc/ChangeLog:
2020-04-08  Dennis Zhang  <dennis.zhang@arm.com>

	* config.gcc: Add arm_cde.h.
	* config/arm/arm-c.c (arm_cpu_builtins): Define or undefine
	__ARM_FEATURE_CDE and __ARM_FEATURE_CDE_COPROC.
	* config/arm/arm-cpus.in (cdecp0, cdecp1, ..., cdecp7): New options.
	* config/arm/arm.c (arm_option_reconfigure_globals): Configure
	arm_arch_cde and arm_arch_cde_coproc to store the feature bits.
	* config/arm/arm.h (TARGET_CDE): New macro.
	* config/arm/arm_cde.h: New file.
	* doc/invoke.texi: Document CDE options +cdecp[0-7].
	* doc/sourcebuild.texi (arm_v8m_main_cde_ok): Document new target
	supports option.
	(arm_v8m_main_cde_fp, arm_v8_1m_main_cde_mve): Likewise.

gcc/testsuite/ChangeLog:
2020-04-08  Dennis Zhang  <dennis.zhang@arm.com>

	* gcc.target/arm/pragma_cde.c: New test.
	* lib/target-supports.exp (arm_v8m_main_cde_ok): New target support
	option.
	(arm_v8m_main_cde_fp, arm_v8_1m_main_cde_mve): Likewise.

For -fsanitize=vptr, we insert a NULL store into the vptr instead of just
adding a CLOBBER of this.  build_clobber_this makes the CLOBBER conditional
on in_charge (implicit) parameter whenever CLASSTYPE_VBASECLASSES, but when
adding this conditionalization to the -fsanitize=vptr code in PR87095,
I wanted it to catch some more cases when the class has CLASSTYPE_VBASECLASSES,
but the vptr is still not shared with something else, otherwise the
sanitization would be less effective.
The following testcase shows that the chosen test that CLASSTYPE_PRIMARY_BINFO
is non-NULL and has BINFO_VIRTUAL_P set wasn't sufficient,
the D class has still sizeof(D) == sizeof(void*) and thus contains just
a single vptr, but while in B::~B() this results in the vptr not being
cleared, in C::~C() this condition isn't true, as CLASSTYPE_PRIMARY_BINFO
in that case is B and is not BINFO_VIRTUAL_P, so it clears the vptr, but the
D::~D() dtor after invoking C::~C() invokes A::~A() with an already cleared
vptr, which is then reported.
The following patch is just a shot in the dark, keep looking through
CLASSTYPE_PRIMARY_BINFO until we find BINFO_VIRTUAL_P, but it works on the
existing testcase as well as this new one.

2020-04-08  Jakub Jelinek  <jakub@redhat.com>

	PR c++/94325
	* decl.c (begin_destructor_body): For CLASSTYPE_VBASECLASSES class
	dtors, if CLASSTYPE_PRIMARY_BINFO is non-NULL, but not BINFO_VIRTUAL_P,
	look at CLASSTYPE_PRIMARY_BINFO of its BINFO_TYPE if it is not
	BINFO_VIRTUAL_P, and so on.

	* g++.dg/ubsan/vptr-15.C: New test.

Here we ICE because early_check_defaulted_comparison passed a null
ctx to same_type_p.  The attached test is ill-formed according to
[class.compare.default]/1, so fixed by detecting this case early.

	PR c++/94478 - ICE with defaulted comparison operator
	* method.c (early_check_defaulted_comparison): Give an error when the
	context is null.

	* g++.dg/cpp2a/spaceship-err4.C: New test.

Since commit 2f6d557ff82876432be76b1892c6c3783c0095f4 AKA SVN-r269586,
the inform() message suggesting the use of -flax-vector-conversions
has had quotes around the option name, but the testcase still expected
the message without the quotes.  This patch adds to the expected
compiler output the quotes that are now issues.


for  gcc/testsuite/ChangeLog

	* gcc.target/arm/polytypes.c: Add quotes around
	-flax-vector-conversions.

The following testcase shows two separate issues caused by the cselib
changes.
One is that through the cselib sp tracking improvements on
... r12 = rsp; rsp -= 8; push cst1; push cst2; push cst3; call
rsp += 32; rsp -= 8; push cst4; push cst5; push cst6; call
rsp += 32; rsp -= 8; push cst7; push cst8; push cst9; call
rsp += 32
reload_cse_simplify_set decides to optimize the rsp += 32 insns
into rsp = r12 because cselib figures that the r12 register holds the right
value.  From the pure cost perspective that seems like a win and on its own
at least for -Os that would be beneficial, except that there are those
rsp -= 8 stack adjustments after it, where rsp += 32; rsp -= 8; is optimized
into rsp += 24; by the csa pass, but rsp = r12; rsp -= 8 can't.  Dunno
what to do about this part, the PR has a hack in a comment.

Anyway, the following patch fixes the other part, which isn't a missed
optimization, but a wrong-code issue.  The problem is that the pushes of
constant are on x86 represented through PRE_MODIFY and while
move2add_note_store has some code to handle {PRE,POST}_{INC,DEC} without
REG_INC note, it doesn't handle {PRE,POST}_MODIFY (that would be enough
to fix this testcase).  But additionally it looks misplaced, because
move2add_note_store is only called on the rtxes that are stored into,
while RTX_AUTOINC can happen not just in those, but anywhere else in the
instruction (e.g. pop insn can have autoinc in the SET_SRC MEM).
REG_INC note seems to be required for any autoinc except for stack pointer
autoinc which doesn't have those notes, so this patch just handles
the sp autoinc after the REG_INC note handling loop.

2020-04-08  Jakub Jelinek  <jakub@redhat.com>

	PR rtl-optimization/94516
	* postreload.c: Include rtl-iter.h.
	(reload_cse_move2add): Handle SP autoinc here by FOR_EACH_SUBRTX_VAR
	looking for all MEMs with RTX_AUTOINC operand.
	(move2add_note_store): Remove {PRE,POST}_{INC,DEC} handling.

	* gcc.dg/torture/pr94516.c: New test.

        * omp-grid.c (grid_eliminate_combined_simd_part): Use
        OMP_CLAUSE_CODE to access the omp clause code.

The following change accidentally got committed in the previous
commit, r10-7614-g13e41d8b,
among the intended changes. Hence:

Revert:
	gcc/
	* omp-grid.c (grid_eliminate_combined_simd_part): Use
	OMP_CLAUSE_CODE to access the omp clause code.

	gcc/c/
	PR middle-end/94120
	* c-decl.c (c_check_in_current_scope): New function.
	* c-tree.h (c_check_in_current_scope): Declare it.
	* c-parser.c (c_parser_oacc_declare): Add check that variables
	are declared in the same scope as the directive. Fix handling
	of namespace vars.

	gcc/cp/
	PR middle-end/94120
	* paser.c (cp_parser_oacc_declare): Add check that variables
	are declared in the same scope as the directive.

	gcc/testsuite/
	PR middle-end/94120
	* c-c++-common/goacc/declare-pr94120.c: New.
	* g++.dg/declare-pr94120.C: New.

	libgomp/testsuite/
	PR middle-end/94120
	* libgomp.oacc-c++/declare-pr94120.C: New.

This moves WARN_DFLAGS from GDCFLAGS to AM_DFLAGS so it is always
included in the build and testsuite of libphobos.  Currently, this
doesn't happen as GDCFLAGS is overriden by it being set at the
top-level.

libphobos/ChangeLog:

	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* configure.ac: Substite WARN_DFLAGS independently of GDCFLAGS.
	* libdruntime/Makefile.am: Add WARN_DFLAGS to AM_DFLAGS.
	* libdruntime/Makefile.in: Regenerate.
	* src/Makefile.am: Add WARN_DFLAGS to AM_DFLAGS.
	* src/Makefile.in: Regenerate.
	* testsuite/Makefile.in: Regenerate.
	* testsuite/testsuite_flags.in: Add WARN_DFLAGS to --gdcflags.

The problem here was that cp_parser_requires_expression committing to a
tentative parse confused cp_parser_decltype_expr, which needs to still be
tentative.  The only reason to commit here is to get syntax errors within
the requires-expression, which we can still do when the commit is firewalled
from the enclosing context.

gcc/cp/ChangeLog
2020-04-07  Jason Merrill  <jason@redhat.com>

	PR c++/94480
	* parser.c (cp_parser_requires_expression): Use tentative_firewall.

Improves the versioning of IeeeFlags and FloatingPointControl code and
unit-tests, making it clearer which targets can and cannot support it.

Reviewed-on: https://github.com/dlang/phobos/pull/7435

	PR rtl-optimization/92264
	* config/h8300/h8300.md (mov;add peephole2): Avoid applying when
	the destination is the stack pointer.

Here the 'decltype' is missing '(auto)', so open_paren was NULL, and trying
to get its location is a SEGV.  Using matching_parens avoids that problem.

gcc/cp/ChangeLog
2020-04-07  Jason Merrill  <jason@redhat.com>

	PR c++/94481
	* parser.c (cp_parser_placeholder_type_specifier): Use
	matching_parens.

The following testcase ICEs on armv7hl-linux-gnueabi.
try_combine is called on:
(gdb) p debug_rtx (i3)
(insn 20 12 22 2 (set (mem/c:SI (plus:SI (reg/f:SI 102 sfp)
                (const_int -4 [0xfffffffffffffffc])) [1 x+0 S4 A32])
        (reg:SI 125)) "pr94291.c":7:8 241 {*arm_movsi_insn}
     (expr_list:REG_DEAD (reg:SI 125)
        (nil)))
(gdb) p debug_rtx (i2)
(insn 12 7 20 2 (parallel [
            (set (reg:CC 100 cc)
                (compare:CC (reg:SI 121 [ <retval> ])
                    (const_int 0 [0])))
            (set (reg:SI 125)
                (reg:SI 121 [ <retval> ]))
        ]) "pr94291.c":7:8 248 {*movsi_compare0}
     (expr_list:REG_UNUSED (reg:CC 100 cc)
        (nil)))
and tries to recognize cc = r121 cmp 0; [sfp-4] = r121 parallel,
but that isn't recognized, so it splits it into two: split_i2i3
[sfp-4] = r121 followed by cc = r121 cmp 0 which is recognized, but
ICEs because the code below insist that the SET_DEST of newi2pat
(or first set in PARALLEL thereof) must be a REG or SUBREG of REG,
but it is a MEM in this case.  I don't see any condition that would
guarantee that, perhaps for the swap_i2i3 case it was somehow guaranteed.

As the code just wants to update LOG_LINKS and LOG_LINKS are only for
registers, not for MEM or anything else, the patch just doesn't update those
if it isn't a REG or SUBREG of REG.

2020-04-07  Jakub Jelinek  <jakub@redhat.com>

	PR rtl-optimization/94291
	PR rtl-optimization/84169
	* combine.c (try_combine): For split_i2i3, don't assume SET_DEST
	must be a REG or SUBREG of REG; if it is not one of these, don't
	update LOG_LINKs.

	* gcc.dg/pr94291.c: New test.

With this patch we get rid of the usage of the glibc-internal symbol
__tls_get_addr_internal.

If build with multilib, the file
gcc/libphobos/libdruntime/config/systemz/get_tls_offset.S is used
for both configurations: systemz and s390.
Therefore both implementations are now in the systemz file which
uses an "#ifdef __s390x__" in order to distinguish both cases.
The s390 file is just including the systemz one.

libphobos/ChangeLog:

2020-04-07  Robin Dapp  <rdapp@linux.ibm.com>
            Stefan Liebler  <stli@linux.ibm.com>

	* configure: Regenerate.
	* libdruntime/Makefile.am: Add s390x and s390.
	* libdruntime/Makefile.in: Regenerate.
	* libdruntime/config/s390/get_tls_offset.S: New file.
	* libdruntime/config/systemz/get_tls_offset.S: New file.
	* libdruntime/gcc/sections/elf_shared.d: Use ibmz_get_tls_offset.
	* m4/druntime/cpu.m4: Add s390x and s390.

	PR libgcc/94513
	* generic-morestack.c: Give up trying to use __mmap/__munmap, use
	syscall instead.

When gimplifying an address operand we may expose an indirect
ref via DECL_VALUE_EXPR for example.  This is dealt with in the
code already but it fails to consider that INDIRECT_REFs get
gimplified to MEM_REFs.

Fixed which makes the ICE observed on x86_64-netbsd go away.

2020-04-07  Richard Biener  <rguenther@suse.de>

	PR middle-end/94479
	* gimplify.c (gimplify_addr_expr): Also consider generated
	MEM_REFs.

	* gcc.dg/torture/pr94479.c: New testcase.

2020-04-01  Fritz Reese  <foreese@gcc.gnu.org>
	    Steven G. Kargl  <kargl@gcc.gnu.org>

gcc/fortran/ChangeLog

	PR fortran/93871
	* gfortran.h (GFC_ISYM_ACOSD, GFC_ISYM_ASIND, GFC_ISYM_ATAN2D,
	GFC_ISYM_ATAND, GFC_ISYM_COSD, GFC_ISYM_COTAND, GFC_ISYM_SIND,
	GFC_ISYM_TAND): New.
	* intrinsic.c (add_functions): Remove check for flag_dec_math.
	Give degree trig functions simplification and name resolution
	functions (e.g, gfc_simplify_atrigd () and gfc_resolve_atrigd ()).
	(do_simplify): Remove special casing of degree trig functions.
	* intrinsic.h (gfc_simplify_acosd, gfc_simplify_asind,
	gfc_simplify_atand, gfc_simplify_cosd, gfc_simplify_cotand,
	gfc_simplify_sind, gfc_simplify_tand, gfc_resolve_trigd2): Add new
	prototypes.
	(gfc_simplify_atrigd, gfc_simplify_trigd, gfc_resolve_cotan,
	resolve_atrigd): Remove prototypes of deleted functions.
	* iresolve.c (is_trig_resolved, copy_replace_function_shallow,
	gfc_resolve_cotan, get_radians, get_degrees, resolve_trig_call,
	gfc_resolve_atrigd, gfc_resolve_atan2d): Delete functions.
	(gfc_resolve_trigd, gfc_resolve_trigd2): Resolve to library functions.
	* simplify.c (rad2deg, deg2rad, gfc_simplify_acosd, gfc_simplify_asind,
	gfc_simplify_atand, gfc_simplify_atan2d, gfc_simplify_cosd,
	gfc_simplify_sind, gfc_simplify_tand, gfc_simplify_cotand): New
	functions.
	(gfc_simplify_atan2): Fix error message.
	(simplify_trig_call, gfc_simplify_trigd, gfc_simplify_atrigd,
	radians_f): Delete functions.
	* trans-intrinsic.c: Add LIB_FUNCTION decls for sind, cosd, tand.
	(rad2deg, gfc_conv_intrinsic_atrigd, gfc_conv_intrinsic_cotan,
	gfc_conv_intrinsic_cotand, gfc_conv_intrinsic_atan2d): New functions.
	(gfc_conv_intrinsic_function): Handle ACOSD, ASIND, ATAND, COTAN,
	COTAND, ATAN2D.
	* trigd_fe.inc: New file. Included by simplify.c to implement
	simplify_sind, simplify_cosd, simplify_tand with code common to the
	libgfortran implementation.

gcc/testsuite/ChangeLog

	PR fortran/93871
	* gfortran.dg/dec_math.f90: Extend coverage to real(10) and real(16).
	* gfortran.dg/dec_math_2.f90: New test.
	* gfortran.dg/dec_math_3.f90: Likewise.
	* gfortran.dg/dec_math_4.f90: Likewise.
	* gfortran.dg/dec_math_5.f90: Likewise.

libgfortran/ChangeLog

	PR fortran/93871
	* Makefile.am, Makefile.in: New make rule for intrinsics/trigd.c.
	* gfortran.map: New routines for {sind, cosd, tand}X{r4, r8, r10, r16}.
	* intrinsics/trigd.c, intrinsics/trigd_lib.inc, intrinsics/trigd.inc:
	New files. Defines native degree-valued trig functions.

The following testcase ICEs on aarch64 apparently since the introduction of
the aarch64 port.  The reason is that the {ashl,ashr,lshr}<mode>3 expanders
completely unnecessarily FAIL; if operands[2] is something other than
a CONST_INT or REG or MEM and the middle-end code can't cope with the
pattern giving up in these cases.  All the expanders use general_operand
predicate for the shift amount operand, but then have just a special case
for CONST_INT (if in-bound, emit an immediate shift, otherwise force into
REG), or MEM (force into REG), or REG (that is the case it handles).
In the testcase, operands[2] is a lowpart SUBREG of a REG, which is valid
general_operand.
I don't see any reason what is magic about MEMs that it should be forced
into REG and others like SUBREGs that it shouldn't, there isn't even a
reason to check for !REG_P because force_reg will do nothing if the operand
is already a REG, and otherwise can handle general_operand just fine.

2020-04-07  Jakub Jelinek  <jakub@redhat.com>

	PR target/94488
	* config/aarch64/aarch64-simd.md (ashl<mode>3, lshr<mode>3,
	ashr<mode>3): Force operands[2] into reg whenever it is not CONST_INT.
	Assume it is a REG after that instead of testing it and doing FAIL
	otherwise.  Formatting fix.

	* gcc.c-torture/compile/pr94488.c: New test.