gcc/testsuite:
	* lib/target-supports.exp (check_compile): Handle D.
	(check_effective_target_d_runtime): New proc.
	* lib/gdc-dg.exp (gdc-dg-test): Demote link and run tests to
	compile unless d_runtime.
	* gdc.dg/runnable.d: Skip unless d_runtime.
	* gdc.dg/lto/lto.exp: Require d_runtime to run tests.

	gcc:
	* doc/sourcebuild.texi (Effective-Target Keywords, Environment
	attributes): Document d_runtime.

From-SVN: r266438

2018-11-25  Vladimir Makarov  <vmakarov@redhat.com>

	PR bootstrap/88157
	* ira-costs.c (record_operand_costs): Initiate register move cost
	for mode.

From-SVN: r266435

From-SVN: r266434

gcc/d/ChangeLog:

2018-11-24  Iain Buclaw  <ibuclaw@gdcproject.org>

	PR d/87866
	* d-incpath.cc (add_globalpaths): Use lrealpath to get canonical name.
	(add_filepaths): Likewise.

From-SVN: r266429

2018-11-24  Paul Thomas  <pault@gcc.gnu.org>

	PR fortran/88143
	* resolve.c (resolve_variable): Check for associate names with
	NULL target.

2018-11-24  Paul Thomas  <pault@gcc.gnu.org>

	PR fortran/88143
	* gfortran.dg/associate_46.f90: New test.

From-SVN: r266428

	PR fortran/888143
	* resolve.c (resolve_variable): Check for associate names with
	NULL target.

2018-11-24  Paul Thomas  <pault@gcc.gnu.org>

	PR fortran/888143
	* gfortran.dg/associate_46.f90: New test.

From-SVN: r266427

	PR rtl-optimization/87468
	* tree-ssa-threadupdate.c (create_block_for_threading): Clear
	EDGE_IGNORE on all outgoing edges of the duplicate block.

From-SVN: r266426

From-SVN: r266425

2018-11-23  Vladimir Makarov  <vmakarov@redhat.com>

	PR bootstrap/88157
	* ira-costs.c (record_operand_costs): Use bigger hard reg class if
	its mode does not fit to the original class.

From-SVN: r266422

2018-11-23  Vladimir Makarov  <vmakarov@redhat.com>

	* gcc.target/powerpc/pr70669.c: Use unary minus instead of
	addition.

From-SVN: r266421

re PR tree-optimization/87756 (missing unterminated argument warning using address of a constant character)

	PR tree-optimization/87756
	* gcc.dg/builtin-memchr-2.c: Scan the gimple dump instead of
	optimized.
	* gcc.dg/builtin-memchr-3.c: Likewise.

From-SVN: r266420

With multiple threads, using an unprotected static variable to check
whether recursion has occured isn't valid, as one thread might have
modified the variable, thus causing another thread to incorrectly
conclude that recursion has occured.  This patch avoids this problem
by using a thread-specific variable for the recursion check.

Regtested on x86_64-pc-linux-gnu.

libgfortran/ChangeLog:

2018-11-23  Janne Blomqvist  <jb@gcc.gnu.org>

	* runtime/error.c (MAGIC): Remove.
	(recursion_key): New variable.
	(recursion_check): Use thread-specific variable for recursion
	check if threads are active.
	(constructor_recursion_check): New function.
	(destructor_recursion_check): New funcion.

From-SVN: r266419

PR tree-optimization/87756 - missing unterminated argument warning using address of a constant character

gcc/ChangeLog:

	PR tree-optimization/87756
	* expr.c (string_constant): Synthesize a string literal from
	the address of a constant character.
	* tree.c (build_string_literal): Add an argument.
	* tree.h (build_string_literal): Same.

gcc/testsuite/ChangeLog:

	PR tree-optimization/87756
	* gcc.dg/builtin-memchr-2.c: New test.
	* gcc.dg/builtin-memchr-3.c: Same.
	* gcc.dg/warn-sprintf-no-nul-2.c: Same.

From-SVN: r266418

gcc/c/ChangeLog:

	PR testsuite/88098
	* c-typeck.c (convert_arguments): Call builtin_decl_explicit instead.
	(maybe_warn_builtin_no_proto_arg): Handle short enum to int promotion.

gcc/testsuite/ChangeLog:

	PR testsuite/88098
	* gcc.dg/Wbuiltin-declaration-mismatch-4.c: Adjust.
	* gcc.dg/Wbuiltin-declaration-mismatch-5.c: New test.
	* gcc.dg/torture/pr67222.c: Adjust.

From-SVN: r266417

2018-11-23  Edward Smith-Rowland  <3dw4rd@verizon.net>

	Implement P0415 More constexpr for std::complex.
	* include/std/complex (conj(complex<Tp>), norm(complex<Tp>)): Constexpr;
	(real(Tp), imag(Tp)): Constexpr;
	(operator@=(Tp), operator@=(complex<Tp>)): Constexpr;
	(operator@(Tp,complex<Tp>), operator@(complex<Tp>,Tp)
	operator@(complex<Tp>,complex<Tp>)): Constexpr.
	* testsuite/26_numerics/complex/comparison_operators/
	more_constexpr.cc: New test.
	* testsuite/26_numerics/complex/operators/more_constexpr.cc: New test.
	* testsuite/26_numerics/complex/requirements/
	more_constexpr.cc: New test.
	* testsuite/26_numerics/complex/value_operations/
	more_constexpr.cc: New test.
	* testsuite/26_numerics/headers/complex/synopsis.cc:
	Add _GLIBCXX20_CONSTEXPR to applicable operators; Add missing proj().
	* testsuite/26_numerics/headers/complex/synopsis.cc:
	Add _GLIBCXX20_CONSTEXPR to relevant decls.

From-SVN: r266416

2018-11-23  Christoph Muellner <christoph.muellner@theobroma-system.com>

	* config/aarch64/aarch64-cores.def: Define emag.
	* config/aarch64/aarch64-tune.md: Regenerated with emag.
	* config/aarch64/aarch64.c (emag_tunings): New struct.
	* doc/invoke.texi: Document mtune value.

From-SVN: r266415

2018-11-23  Christoph Muellner  <christoph.muellner@theobroma-systems.com>
	    Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

	* config/aarch64/aarch64.c (xgene1_tunings): Optimize Xgene1 tunings
	for GCC 9.

Co-Authored-By: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

From-SVN: r266414

2018-11-23  Christoph Muellner  <christoph.muellner@theobroma-systems.com>
            Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

	* config/aarch64/aarch64.c (xgene1_tunings): Add Xgene1 specific
	prefetch tunings.

Co-Authored-By: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

From-SVN: r266413

2018-11-23  Christoph Muellner  <christoph.muellner@theobroma-systems.com>
            Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

	* config/aarch64/aarch64.c (xgene1_addrcost_table): Correct the post modify
	costs.

Co-Authored-By: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

From-SVN: r266412

2018-11-23  Christoph Muellner <christoph.muellner@theobroma-system.com>

	* config/arm/aarch-cost-tables.h (xgene1_extra_costs): Update the cost table
	for Xgene1.

From-SVN: r266411

2018-11-23  Martin Sebor  <msebor@redhat.com>
	    Jonathan Wakely  <jwakely@redhat.com>

	PR libstdc++/65229
	* python/libstdcxx/v6/printers.py (StdBitsetPrinter): Handle
	exception thrown for std::bitset<0>.
	* testsuite/libstdc++-prettyprinters/simple.cc: Test std::bitset<0>.

Co-Authored-By: Jonathan Wakely <jwakely@redhat.com>

From-SVN: r266409

The pretty printer for std::any fails when the contained value is a
locally-defined type, because the name in the debuginfo has
cv-qualifiers and ptr-declarators in different positions. The unexpected
format confuses the printer. This makes the printer's regex handle
either format.

This isn't a complete fix because looking up the contained type fails
when there are two types with the same name (defined in different local
scopes). This applies to all closure types defined in a given function,
as they all appear as "func()::lambda" in the debuginfo names.

	PR libstdc++/87308 (partial)
	* python/libstdcxx/v6/printers.py (StdExpAnyPrinter): Adjust regex to
	work around PR 88166.
	* testsuite/libstdc++-prettyprinters/cxx17.cc: Test std::any
	containing a local type.

From-SVN: r266408

2018-11-23  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/88149
	* tree-vect-slp.c (vect_slp_analyze_node_operations): Detect
	the case where there are two different def types for the
	same operand at different operand position in the same stmt.

	* g++.dg/torture/pr88149.C: New testcase.

From-SVN: r266406

This patch removes some of the machine mode checks from the arm backend when
emitting instructions by using the '@' construct (Parameterized Names[2]). It
is based on the previous AArch64 patch[1].

[1] https://gcc.gnu.org/ml/gcc-patches/2018-07/msg00673.html
[2] https://gcc.gnu.org/onlinedocs/gccint/Parameterized-Names.html#Parameterized-Names


2018-23-11  Mihail Ionescu  <mihail.ionescu@arm.com>

	* config/arm/arm.c (arm_expand_compare_and_swap): Simplify and call
	gen_atomic_compare_swap_1.
	(arm_evpc_neon_vuzp): Likewise gen_neon_vuzp_internal.
	(arm_evpc_neon_vtrn): Likewise gen_neon_vtrn_internal.
	(arm_evpc_neon_vext): Likewise gen_neon_vext_internal.
	(arm_evpc_neon_vzip): Likewise gen_neon_vzip_internal.
	(arm_evpc_neon_vrev): Replace the function pointer and simplify the mode
	checks.
	* config/arm/arm.md (neon_vext<mode>),
	(neon_vrev64<mode>, neon_vrev32<mode>),
	(neon_vrev16<mode>, neon_vtrn<mode>_internal),
	(neon_vzip<mode>_internal, neon_vuzp<mode>_internal): Add an '@'character
	before the pattern name.
	* config/arm/sync.md:
	(atomic_compare_and_swap<CCSI:arch><NARROW:mode>_1),
	(atomic_compare_and_swap<CCSI:arch><SIDI:mode>_1): Likewise.

From-SVN: r266404

re PR tree-optimization/86614 (duplicate -Warray-bounds for a strncpy  call with out-of-bounds offset)

	PR tree-optimization/86614
	* gimple-ssa-warn-restrict.c (maybe_diag_offset_bounds): Return early
	if TREE_NO_WARNING is set on ref.ref.

	* c-c++-common/Warray-bounds-2.c (wrap_strncpy_dstarray_diff_neg,
	call_strncpy_dstarray_diff_neg): Don't expect late -Warray-bounds
	warnings, just early ones from FE.  Remove dg-prune-output.
	* c-c++-common/Warray-bounds-6.c: New test.

From-SVN: r266403

2018-11-22  Sandra Loosemore  <sandra@codesourcery.com>
	    Alan Coopersmith  <alan.coopersmith@oracle.com>

	PR c/53608

	gcc/
	* doc/extend.texi (Designated Inits): Clarify handling of multiple
	initializers for unions.

Co-Authored-By: Alan Coopersmith <alan.coopersmith@oracle.com>

From-SVN: r266402

From-SVN: r266400

	* lang.opt (fpad-source): New option.
	* scanner.c (load_line): Don't pad fixed form lines if
	!flag_pad_source.
	* invoke.texi (-fno-pad-source): Document.

	* gfortran.dg/pad_source_1.f: New test.
	* gfortran.dg/pad_source_2.f: New test.
	* gfortran.dg/pad_source_3.f: New test.
	* gfortran.dg/pad_source_4.f: New test.
	* gfortran.dg/pad_source_5.f: New test.

From-SVN: r266397

	PR lto/88142
	* ipa-devirt.c (type_variants_equivalent_p): Drop warn and warned
	parameters; do not warn here.
	(odr_subtypes_equivalent_p): Likewise.
	(warn_odr): Fix typo.
	(warn_types_mismatch): Do not output confused warnings on integer types.
	(odr_types_equivalent_p): Update.

	* g++.dg/lto/odr-5_0.C: New testcase.
	* g++.dg/lto/odr-5_1.C: New testcase.

From-SVN: r266396

	* lto.c (cmp_type_location): Remove.
	(lto_read_decls): Do not allocate odr_types.

From-SVN: r266395

	* config/i386/i386.c (ix86_option_override_internal,
	ix86_can_inline_p, classify_argument, construct_container,
	ix86_expand_prologue, ix86_expand_split_stack_prologue,
	ix86_expand_carry_flag_compare, expand_set_or_movmem_via_loop,
	expand_setmem_epilogue_via_loop, promote_duplicated_reg,
	ix86_expand_set_or_movmem, ix86_init_builtins_va_builtins_abi):
	Formatting fixes.

From-SVN: r266391

	* config/i386/i386.c (ix86_option_override_internal): For
	stack_protector_guard related options, use opts_set->x_ instead
	of global_options_set. and prefix options with opts->x_ .  Move
	defaults for offset and reg into else block.

From-SVN: r266390

	* config/i386/i386.c (ix86_check_avx_upper_register):
	Return true for all SSE registers with mode bitsize > 128.

From-SVN: r266389

	* g++.dg/lto/odr-2_0.C: Drop dg-lto-options.
	* g++.dg/lto/odr-3_0.C: Likewise; harden for optimizing compilatoin.

From-SVN: r266388

	PR tree-optimization/85794
	* gcc.dg/vect/O3-pr85794.c: New test.

From-SVN: r266387

2018-11-22  Marc Glisse  <marc.glisse@inria.fr>

	PR libstdc++/87106
	* include/bits/stl_algobase.h: Include <type_traits>.
	(__niter_base): Add noexcept specification.
	* include/bits/stl_deque.h: Include <bits/stl_uninitialized.h>.
	(__is_trivially_relocatable): Specialize for deque.
	* include/bits/stl_iterator.h: Include <type_traits>.
	(__niter_base): Add noexcept specification.
	* include/bits/stl_uninitialized.h (__is_trivially_relocatable):
	Add parameter for meta-programming.
	(__relocate_a_1, __relocate_a): Add noexcept specification.
	* include/bits/stl_vector.h (__use_relocate): Test __relocate_a.

From-SVN: r266386

2018-11-22  Vladimir Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/87718
	* ira-costs.c: Remove trailing white-spaces.
	(record_operand_costs): Add a special treatment for moves
	involving a hard register.

2018-11-22  Vladimir Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/87718
	* gcc.target/i386/pr82361-1.c: Check only the first operand of
	moves.

From-SVN: r266385

	* config/i386/i386.c (ix86_avx_emit_vzeroupper): Remove.
	(ix86_emit_mode_set) <case AVX_U128>: Emit vzeroupper here.

From-SVN: r266382

2018-11-22  Martin Liska  <mliska@suse.cz>

	* common/config/i386/i386-common.c (processor_names): Add
	static assert and add missing "znver2".
	(ix86_get_valid_option_values): Add checking assert for null
	values and add "native" value if feasible.
	* config/i386/i386.h: Do not declare size of processor_names.
	* common/config/i386/i386-common.c:
	* config/i386/i386.c: Add static assert for size
	of processor_cost_table.

From-SVN: r266381

In case of high register pressure in PIC mode, address of the stack
protector's guard can be spilled on ARM targets as shown in PR85434,
thus allowing an attacker to control what the canary would be compared
against. ARM does lack stack_protect_set and stack_protect_test insn
patterns, defining them does not help as the address is expanded
regularly and the patterns only deal with the copy and test of the
guard with the canary.

This problem does not occur for x86 targets because the PIC access and
the test can be done in the same instruction. Aarch64 is exempt too
because PIC access insn pattern are mov of UNSPEC which prevents it from
the second access in the epilogue being CSEd in cse_local pass with the
first access in the prologue.

The approach followed here is to create new "combined" set and test
standard pattern names that take the unexpanded guard and do the set or
test. This allows the target to use an opaque pattern (eg. using UNSPEC)
to hide the individual instructions being generated to the compiler and
split the pattern into generic load, compare and branch instruction
after register allocator, therefore avoiding any spilling. This is here
implemented for the ARM targets. For targets not implementing these new
standard pattern names, the existing stack_protect_set and
stack_protect_test pattern names are used.

To be able to split PIC access after register allocation, the functions
had to be augmented to force a new PIC register load and to control
which register it loads into. This is because sharing the PIC register
between prologue and epilogue could lead to spilling due to CSE again
which an attacker could use to control what the canary gets compared
against.

2018-11-22  Thomas Preud'homme  <thomas.preudhomme@linaro.org>

    gcc/
    PR target/85434
    * target-insns.def (stack_protect_combined_set): Define new standard
    pattern name.
    (stack_protect_combined_test): Likewise.
    * cfgexpand.c (stack_protect_prologue): Try new
    stack_protect_combined_set pattern first.
    * function.c (stack_protect_epilogue): Try new
    stack_protect_combined_test pattern first.
    * config/arm/arm.c (require_pic_register): Add pic_reg and compute_now
    parameters to control which register to use as PIC register and force
    reloading PIC register respectively.  Insert in the stream of insns if
    possible.
    (legitimize_pic_address): Expose above new parameters in prototype and
    adapt recursive calls accordingly.  Use pic_reg if non null instead of
    cached one.
    (arm_load_pic_register): Add pic_reg parameter and use it if non null.
    (arm_legitimize_address): Adapt to new legitimize_pic_address
    prototype.
    (thumb_legitimize_address): Likewise.
    (arm_emit_call_insn): Adapt to require_pic_register prototype change.
    (arm_expand_prologue): Adapt to arm_load_pic_register prototype change.
    (thumb1_expand_prologue): Likewise.
    * config/arm/arm-protos.h (legitimize_pic_address): Adapt to prototype
    change.
    (arm_load_pic_register): Likewise.
    * config/arm/predicated.md (guard_addr_operand): New predicate.
    (guard_operand): New predicate.
    * config/arm/arm.md (movsi expander): Adapt to legitimize_pic_address
    prototype change.
    (builtin_setjmp_receiver expander): Adapt to thumb1_expand_prologue
    prototype change.
    (stack_protect_combined_set): New expander..
    (stack_protect_combined_set_insn): New insn_and_split pattern.
    (stack_protect_set_insn): New insn pattern.
    (stack_protect_combined_test): New expander.
    (stack_protect_combined_test_insn): New insn_and_split pattern.
    (arm_stack_protect_test_insn): New insn pattern.
    * config/arm/thumb1.md (thumb1_stack_protect_test_insn): New insn pattern.
    * config/arm/unspecs.md (UNSPEC_SP_SET): New unspec.
    (UNSPEC_SP_TEST): Likewise.
    * doc/md.texi (stack_protect_combined_set): Document new standard
    pattern name.
    (stack_protect_set): Clarify that the operand for guard's address is
    legal.
    (stack_protect_combined_test): Document new standard pattern name.
    (stack_protect_test): Clarify that the operand for guard's address is
    legal.

    gcc/testsuite/
    PR target/85434
    * gcc.target/arm/pr85434.c: New test.

From-SVN: r266379