This patch adds new utility functions for manipulating REG_ARGS_SIZE
notes and allows the notes to carry polynomial as well as constant sizes.

The code was inconsistent about whether INT_MIN or HOST_WIDE_INT_MIN
should be used to represent an unknown size.  The patch uses
HOST_WIDE_INT_MIN throughout.

2017-12-21  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* rtl.h (get_args_size, add_args_size_note): New functions.
	(find_args_size_adjust): Return a poly_int64 rather than a
	HOST_WIDE_INT.
	(fixup_args_size_notes): Likewise.  Make the same change to the
	end_args_size parameter.
	* rtlanal.c (get_args_size, add_args_size_note): New functions.
	* builtins.c (expand_builtin_trap): Use add_args_size_note.
	* calls.c (emit_call_1): Likewise.
	* explow.c (adjust_stack_1): Likewise.
	* cfgcleanup.c (old_insns_match_p): Update use of
	find_args_size_adjust.
	* combine.c (distribute_notes): Track polynomial arg sizes.
	* dwarf2cfi.c (dw_trace_info): Change beg_true_args_size,
	end_true_args_size, beg_delay_args_size and end_delay_args_size
	from HOST_WIDE_INT to poly_int64.
	(add_cfi_args_size): Take the args_size as a poly_int64 rather
	than a HOST_WIDE_INT.
	(notice_args_size, notice_eh_throw, maybe_record_trace_start)
	(maybe_record_trace_start_abnormal, scan_trace, connect_traces): Track
	polynomial arg sizes.
	* emit-rtl.c (try_split): Use get_args_size.
	* recog.c (peep2_attempt): Likewise.
	* reload1.c (reload_as_needed): Likewise.
	* expr.c (find_args_size_adjust): Return the adjustment as a
	poly_int64 rather than a HOST_WIDE_INT.
	(fixup_args_size_notes): Change end_args_size from a HOST_WIDE_INT
	to a poly_int64 and change the return type in the same way.
	(emit_single_push_insn): Track polynomial arg sizes.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255919

This patch changes the "extra" parameters to push_block and
emit_push_insn from int to poly_int64.

2017-12-21  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* expr.h (push_block, emit_push_insn): Change the "extra" parameter
	from HOST_WIDE_INT to poly_int64.
	* expr.c (push_block, emit_push_insn): Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255918

This patch converts the frame allocation code (mostly in function.c)
to use poly_int64 rather than HOST_WIDE_INT for frame offsets and
sizes.

2017-12-21  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* function.h (frame_space): Change start and length from HOST_WIDE_INT
	to poly_int64.
	(get_frame_size): Return the size as a poly_int64 rather than a
	HOST_WIDE_INT.
	(frame_offset_overflow): Take the offset as a poly_int64 rather
	than a HOST_WIDE_INT.
	(assign_stack_local_1, assign_stack_local, assign_stack_temp_for_type)
	(assign_stack_temp): Likewise for the size.
	* function.c (get_frame_size): Return a poly_int64 rather than
	a HOST_WIDE_INT.
	(frame_offset_overflow): Take the offset as a poly_int64 rather
	than a HOST_WIDE_INT.
	(try_fit_stack_local): Take the start, length and size as poly_int64s
	rather than HOST_WIDE_INTs.  Return the offset as a poly_int64_pod
	rather than a HOST_WIDE_INT.
	(add_frame_space): Take the start and end as poly_int64s rather than
	HOST_WIDE_INTs.
	(assign_stack_local_1, assign_stack_local, assign_stack_temp_for_type)
	(assign_stack_temp): Likewise for the size.
	(temp_slot): Change size, base_offset and full_size from HOST_WIDE_INT
	to poly_int64.
	(find_temp_slot_from_address): Handle polynomial offsets.
	(combine_temp_slots): Likewise.
	* emit-rtl.h (rtl_data::x_frame_offset): Change from HOST_WIDE_INT
	to poly_int64.
	* cfgexpand.c (alloc_stack_frame_space): Return the offset as a
	poly_int64 rather than a HOST_WIDE_INT.
	(expand_one_stack_var_at): Take the offset as a poly_int64 rather
	than a HOST_WIDE_INT.
	(expand_stack_vars, expand_one_stack_var_1, expand_used_vars): Handle
	polynomial frame offsets.
	* config/m32r/m32r-protos.h (m32r_compute_frame_size): Take the size
	as a poly_int64 rather than an int.
	* config/m32r/m32r.c (m32r_compute_frame_size): Likewise.
	* config/v850/v850-protos.h (compute_frame_size): Likewise.
	* config/v850/v850.c (compute_frame_size): Likewise.
	* config/xtensa/xtensa-protos.h (compute_frame_size): Likewise.
	* config/xtensa/xtensa.c (compute_frame_size): Likewise.
	* config/pa/pa-protos.h (pa_compute_frame_size): Likewise.
	* config/pa/pa.c (pa_compute_frame_size): Likewise.
	* explow.h (get_dynamic_stack_base): Take the offset as a poly_int64
	rather than a HOST_WIDE_INT.
	* explow.c (get_dynamic_stack_base): Likewise.
	* final.c (final_start_function): Use the constant lower bound
	of the frame size for -Wframe-larger-than.
	* ira.c (do_reload): Adjust for new get_frame_size return type.
	* lra.c (lra): Likewise.
	* reload1.c (reload): Likewise.
	* config/avr/avr.c (avr_asm_function_end_prologue): Likewise.
	* config/pa/pa.h (EXIT_IGNORE_STACK): Likewise.
	* rtlanal.c (get_initial_register_offset): Return the offset as
	a poly_int64 rather than a HOST_WIDE_INT.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255917

This patch makes a few small poly_int64 changes to reload1.c,
mostly related to eliminations.  Again, there's no real expectation
that reload will be used for targets that have polynomial-sized modes,
but it seemed easier to convert it anyway.

2017-12-21  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* reload1.c (elim_table): Change initial_offset, offset and
	previous_offset from HOST_WIDE_INT to poly_int64_pod.
	(offsets_at): Change the target array's element type from
	HOST_WIDE_INT to poly_int64_pod.
	(set_label_offsets, eliminate_regs_1, eliminate_regs_in_insn)
	(elimination_costs_in_insn, update_eliminable_offsets)
	(verify_initial_elim_offsets, set_offsets_for_label)
	(init_eliminable_invariants): Update after above changes.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255916

This patch makes a few small poly_int64 changes to reload.c,
such as in the "decomposition" structure.  In practice, any
port with polynomial-sized modes should be using LRA rather
than reload, but it's easier to convert reload anyway than
to sprinkle to_constants everywhere.

2017-12-21  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* reload.h (reload::inc): Change from an int to a poly_int64_pod.
	* reload.c (combine_reloads, debug_reload_to_stream): Likewise.
	(decomposition): Change start and end from HOST_WIDE_INT
	to poly_int64_pod.
	(decompose, immune_p): Update accordingly.
	(find_inc_amount): Return a poly_int64 rather than an int.
	* reload1.c (inc_for_reload): Take the inc_amount as a poly_int64
	rather than an int.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255915

This patch makes get_inner_reference and ptr_difference_const return the
bit size and bit position as poly_int64s rather than HOST_WIDE_INTS.
The non-mechanical changes were handled by previous patches.

2017-12-21  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* tree.h (get_inner_reference): Return the bitsize and bitpos
	as poly_int64_pods rather than HOST_WIDE_INT.
	* fold-const.h (ptr_difference_const): Return the pointer difference
	as a poly_int64_pod rather than a HOST_WIDE_INT.
	* expr.c (get_inner_reference): Return the bitsize and bitpos
	as poly_int64_pods rather than HOST_WIDE_INT.
	(expand_expr_addr_expr_1, expand_expr_real_1): Track polynomial
	offsets and sizes.
	* fold-const.c (make_bit_field_ref): Take the bitpos as a poly_int64
	rather than a HOST_WIDE_INT.  Update call to get_inner_reference.
	(optimize_bit_field_compare): Update call to get_inner_reference.
	(decode_field_reference): Likewise.
	(fold_unary_loc): Track polynomial offsets and sizes.
	(split_address_to_core_and_offset): Return the bitpos as a
	poly_int64_pod rather than a HOST_WIDE_INT.
	(ptr_difference_const): Likewise for the pointer difference.
	* asan.c (instrument_derefs): Track polynomial offsets and sizes.
	* config/mips/mips.c (r10k_safe_mem_expr_p): Likewise.
	* dbxout.c (dbxout_expand_expr): Likewise.
	* dwarf2out.c (loc_list_for_address_of_addr_expr_of_indirect_ref)
	(loc_list_from_tree_1, fortran_common): Likewise.
	* gimple-laddress.c (pass_laddress::execute): Likewise.
	* gimple-ssa-store-merging.c (find_bswap_or_nop_load): Likewise.
	* gimplify.c (gimplify_scan_omp_clauses): Likewise.
	* simplify-rtx.c (delegitimize_mem_from_attrs): Likewise.
	* tree-affine.c (tree_to_aff_combination): Likewise.
	(get_inner_reference_aff): Likewise.
	* tree-data-ref.c (split_constant_offset_1): Likewise.
	(dr_analyze_innermost): Likewise.
	* tree-scalar-evolution.c (interpret_rhs_expr): Likewise.
	* tree-sra.c (ipa_sra_check_caller): Likewise.
	* tree-vect-data-refs.c (vect_check_gather_scatter): Likewise.
	* ubsan.c (maybe_instrument_pointer_overflow): Likewise.
	(instrument_bool_enum_load, instrument_object_size): Likewise.
	* gimple-ssa-strength-reduction.c (slsr_process_ref): Update call
	to get_inner_reference.
	* hsa-gen.c (gen_hsa_addr): Likewise.
	* sanopt.c (maybe_optimize_ubsan_ptr_ifn): Likewise.
	* tsan.c (instrument_expr): Likewise.
	* match.pd: Update call to ptr_difference_const.

gcc/ada/
	* gcc-interface/trans.c (Attribute_to_gnu): Track polynomial
	offsets and sizes.
	* gcc-interface/utils2.c (build_unary_op): Likewise.

gcc/cp/
	* constexpr.c (check_automatic_or_tls): Track polynomial
	offsets and sizes.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255914

2017-12-21  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* fold-const.c (fold_comparison): Track sizes and offsets as
	poly_int64s rather than HOST_WIDE_INTs when folding address
	comparisons.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255913

This patch makes get_bit_range return the range and position as poly_ints.

2017-12-21  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* expr.h (get_bit_range): Return the bitstart and bitend as
	poly_uint64s rather than unsigned HOST_WIDE_INTs.  Return the bitpos
	as a poly_int64 rather than a HOST_WIDE_INT.
	* expr.c (get_bit_range): Likewise.
	(expand_assignment): Update call accordingly.
	* fold-const.c (optimize_bit_field_compare): Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255912

Previously aarch64_classify_address used an rtx code to distinguish
LDP/STP addresses from normal addresses; the code was PARALLEL
to select LDP/STP and anything else to select normal addresses.
This patch replaces that parameter with a dedicated enum.

The SVE port will add another enum value that didn't map naturally
to an rtx code.

2017-12-21  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* config/aarch64/aarch64-protos.h (aarch64_addr_query_type): New enum.
	(aarch64_legitimate_address_p): Use it instead of an rtx code,
	as an optional final parameter.
	* config/aarch64/aarch64.c (aarch64_classify_address): Likewise.
	(aarch64_legitimate_address_p): Likewise.
	(aarch64_print_address_internal): Take an aarch64_addr_query_type
	instead of an rtx code.
	(aarch64_address_valid_for_prefetch_p): Update calls accordingly.
	(aarch64_legitimate_address_hook_p): Likewise.
	(aarch64_print_ldpstp_address): Likewise.
	(aarch64_print_operand_address): Likewise.
	(aarch64_address_cost): Likewise.
	* config/aarch64/constraints.md (Uml, Umq, Ump, Utq): Likewise.
	* config/aarch64/predicates.md (aarch64_mem_pair_operand): Likewise.
	(aarch64_mem_pair_lanes_operand): Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255911

	* tree-ssa-dom.c (dom_opt_dom_walker::optimize_stmt): Call
	update_stmt_if_modified.

From-SVN: r255910

From-SVN: r255909

	PR tree-optimization/83491
	* tree-ssa-math-opts.c (execute_cse_reciprocals_1): Check for SSA_NAME
	before walking uses.  Improve coding style and comments.

	PR tree-optimization/83491
	* gcc.dg/pr83491.c: Add new test.

From-SVN: r255906

2017-12-20  Tom de Vries  <tom@codesourcery.com>

	* gimple-fold.c (fold_internal_goacc_dim): Simplify.

From-SVN: r255905

2017-12-20  François Dumont  <fdumont@gcc.gnu.org>

	PR libstdc++/82522
	* include/debug/map.h (map::insert(value_type&&))
	(map::insert(const_iterator, value_type&&)): Add overload for rvalues.
	* include/debug/multimap.h (multimap::insert(value_type&&))
	(multimap::insert(const_iterator, value_type&&)): Likewise.
	* include/debug/unordered_map (unordered_map::insert(value_type&&))
	(unordered_map::insert(const_iterator, value_type&&))
	(unordered_multimap::insert(value_type&&))
	(unordered_multimap::insert(const_iterator, value_type&&)): Likewise.
	* testsuite/23_containers/map/modifiers/insert/dr2354.cc (test02): New.
	* testsuite/23_containers/multimap/modifiers/insert/dr2354.cc (test02):
	New.
	* testsuite/23_containers/unordered_map/insert/dr2354.cc (test02): New.
	* testsuite/23_containers/unordered_multimap/insert/dr2354.cc (test02):
	New.

From-SVN: r255904

re PR fortran/83436 (Internal file cannot be accessed by UNFORMATTED data transfer when reading from /dev/urandom)

2017-12-20  Thomas Koenig  <tkoenig@gcc.gnu.org>

	PR fortran/83436
	* gfortran.dg/internal_readwrite_4.f90: New test.

From-SVN: r255902

	PR ipa/83506
	* ipa-fnsummary.c (pass_data_ipa_free_fn_summary): Use 0 for
	todo_flags_finish.
	(pass_ipa_free_fn_summary): Add small_p private data member,
	initialize to false in the ctor.
	(pass_ipa_free_fn_summary::clone,
	pass_ipa_free_fn_summary::set_pass_param,
	pass_ipa_free_fn_summary::gate): New methods.
	(pass_ipa_free_fn_summary::execute): Return TODO_remove_functions
	| TODO_dump_symtab if small_p.
	* passes.def: Add true parm for the existing pass_ipa_free_fn_summary
	entry and add another instance of the pass with false parm after
	ipa-pure-const.
	* ipa-pure-const.c (pass_ipa_pure_const): Don't call
	ipa_free_fn_summary here.

	* gcc.dg/pr83506.c: New test.
	* gcc.dg/ipa/ctor-empty-1.c: Use -fdump-ipa-free-fnsummary1 instead
	of -fdump-ipa-free-fnsummary and scan in free-fnsummary1 instead of
	free-fnsummary dump.

From-SVN: r255901

2017-12-20  Paolo Carlini  <paolo.carlini@oracle.com>

	* gimplify.c (gimplify_return_expr): Remove dead error_mark_node check.

From-SVN: r255900

gcc/testsuite/ChangeLog:

	PR testsuite/83483
	* gcc.dg/memcpy-6.c: Skip for targets other than x86.

From-SVN: r255899

gcc/ChangeLog:

	PR testsuite/83131
	* builtins.c (expand_builtin_strlen): Use get_callee_fndecl.
	(expand_builtin_strcmp): Call maybe_warn_nonstring_arg.	
	(expand_builtin_strncmp): Same.

gcc/testsuite/ChangeLog:

	PR testsuite/83131
	* c-c++-common/attr-nonstring-4.c: New test.

From-SVN: r255898

2017-12-20  Michael Weiser  <michael.weiser@gmx.de>

	PR preprocessor/83492
	* lex.c (search_line_fast) [__ARM_NEON && __ARM_64BIT_STATE]:
	Fix selection of big-endian shift parameters by using
	__ARM_BIG_ENDIAN.

From-SVN: r255896

Make sure that gimple and RTL IRs don't have debug markers before
labels.  When we build the CFG, we move labels before any markers
appearing before them.  Then, make sure we don't mistakenly
reintroduce them.

This reverts some of the complexity that had been brought about by the
initial SFN patches.

for  gcc/ChangeLog

	PR bootstrap/83396
	* cfgexpand.c (label_rtx_for_bb): Revert SFN changes that
	allowed debug stmts before labels.
	(expand_gimple_basic_block): Likewise.
	* gimple-iterator.c (gimple_find_edge_insert_loc): Likewise.
	* gimple-iterator.h (gsi_after_labels): Likewise.
	* tree-cfgcleanup (remove_forwarder_block): Likewise, but
	rename reused variable, and simplify using gsi_move_before.
	* tree-ssa-tail-merge.c (find_duplicate): Likewise.
	* tree-cfg.c (make_edges, cleanup_dead_labels): Likewise.
	(gimple_can_merge_blocks_p, verify_gimple_in_cfg): Likewise.
	(gimple_verify_flow_info, gimple_block_label): Likewise.
	(make_blocks): Move debug markers after adjacent labels.
	* cfgrtl.c (skip_insns_after_block): Revert SFN changes that
	allowed debug insns outside blocks.
	* df-scan.c (df_insn_delete): Likewise.
	* lra-constraints.c (update_ebb_live_info): Likewise.
	* var-tracking.c (get_first_insn, vt_emit_notes): Likewise.
	(vt_initialize, delete_vta_debug_insns): Likewise.
	(reemit_marker_as_note): Drop BB parm.  Adjust callers.

From-SVN: r255895

This patch makes pass_store_merging track polynomial sizes
and offsets.  store_immediate_info remains restricted to stores
with a constant offset and size.

2017-12-20  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* poly-int-types.h (round_down_to_byte_boundary): New macro.
	(round_up_to_byte_boundary): Likewise.
	* expr.h (get_bit_range): Add temporary shim.
	* gimple-ssa-store-merging.c (store_operand_info): Change the
	bitsize, bitpos, bitregion_start and bitregion_end fields from
	unsigned HOST_WIDE_INT to poly_uint64.
	(merged_store_group): Likewise load_align_base.
	(compatible_load_p, compatible_load_p): Update accordingly.
	(imm_store_chain_info::coalesce_immediate_stores): Likewise.
	(split_group, imm_store_chain_info::output_merged_store): Likewise.
	(mem_valid_for_store_merging): Return the bitsize, bitpos,
	bitregion_start and bitregion_end as poly_uint64s rather than
	unsigned HOST_WIDE_INTs.  Track polynomial offsets internally.
	(handled_load): Take the bitsize, bitpos,
	bitregion_start and bitregion_end as poly_uint64s rather than
	unsigned HOST_WIDE_INTs.
	(pass_store_merging::process_store): Update call to
	mem_valid_for_store_merging.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255894

This patch makes get_object_alignment_2 track polynomial offsets
and sizes.  The real work is done by get_inner_reference, but we
then need to handle the alignment correctly.

2017-12-20  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* builtins.c (get_object_alignment_2): Track polynomial offsets
	and sizes.  Update the alignment handling.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255893

This patch makes expand_debug_expr track polynomial memory offsets.
It simplifies the handling of the case in which the reference is not
to the first byte of the base, which seemed non-trivial enough to
make it worth splitting out as a separate patch.

2017-12-20  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* tree.h (get_inner_reference): Add a version that returns the
	offset and size as poly_int64_pods rather than HOST_WIDE_INTs.
	* cfgexpand.c (expand_debug_expr): Track polynomial offsets.  Simply
	the case in which bitpos is not associated with the first byte.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255892

This patch makes get_inner_reference_aff return the size as a
poly_widest_int rather than a widest_int.

2017-12-20  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* tree-affine.h (get_inner_reference_aff): Return the size as a
	poly_widest_int.
	* tree-affine.c (get_inner_reference_aff): Likewise.
	* tree-data-ref.c (dr_may_alias_p): Update accordingly.
	* tree-ssa-loop-im.c (mem_refs_may_alias_p): Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255891

This patch changes the bitpos argument to pointer_may_wrap_p from
HOST_WIDE_INT to poly_int64.  A later patch makes the callers track
polynomial offsets.

2017-12-20  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* fold-const.c (pointer_may_wrap_p): Take the offset as a
	HOST_WIDE_INT rather than a poly_int64.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255890

This patch changes symbol_number::bytepos from a HOST_WIDE_INT
to a poly_int64.  perform_symbolic_merge can cope with symbolic
offsets as long as the difference between the two offsets is
constant.  (This could happen for a constant-sized field that
occurs at a variable offset, for example.)

2017-12-20  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* gimple-ssa-store-merging.c (symbolic_number::bytepos): Change from
	HOST_WIDE_INT to poly_int64_pod.
	(perform_symbolic_merge): Update accordingly.
	(bswap_replace): Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255889

This patch changes the type of aff_tree::offset from widest_int to
poly_widest_int and adjusts the function interfaces in the same way.

2017-12-20  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* tree-affine.h (aff_tree::offset): Change from widest_int
	to poly_widest_int.
	(wide_int_ext_for_comb): Delete.
	(aff_combination_const, aff_comb_cannot_overlap_p): Take the
	constants as poly_widest_int rather than widest_int.
	(aff_combination_constant_multiple_p): Return the multiplier
	as a poly_widest_int.
	(aff_combination_zero_p, aff_combination_singleton_var_p): Handle
	polynomial offsets.
	* tree-affine.c (wide_int_ext_for_comb): Make original widest_int
	version static and add an overload for poly_widest_int.
	(aff_combination_const, aff_combination_add_cst)
	(wide_int_constant_multiple_p, aff_comb_cannot_overlap_p): Take
	the constants as poly_widest_int rather than widest_int.
	(tree_to_aff_combination): Generalize INTEGER_CST case to
	poly_int_tree_p.
	(aff_combination_to_tree): Track offsets as poly_widest_ints.
	(aff_combination_add_product, aff_combination_mult): Handle
	polynomial offsets.
	(aff_combination_constant_multiple_p): Return the multiplier
	as a poly_widest_int.
	* tree-predcom.c (determine_offset): Return the offset as a
	poly_widest_int.
	(split_data_refs_to_components, suitable_component_p): Update
	accordingly.
	(valid_initializer_p): Update call to
	aff_combination_constant_multiple_p.
	* tree-ssa-address.c (addr_to_parts): Handle polynomial offsets.
	* tree-ssa-loop-ivopts.c (get_address_cost_ainc): Take the step
	as a poly_int64 rather than a HOST_WIDE_INT.
	(get_address_cost): Handle polynomial offsets.
	(iv_elimination_compare_lt): Likewise.
	(rewrite_use_nonlinear_expr): Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255888

This patch changes the values returned by
get_addr_base_and_unit_offset from HOST_WIDE_INT to poly_int64.

maxsize in gimple_fold_builtin_memory_op goes from HOST_WIDE_INT
to poly_uint64 (rather than poly_int) to match the previous use
of tree_fits_uhwi_p.

2017-12-20  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* tree-dfa.h (get_addr_base_and_unit_offset_1): Return the offset
	as a poly_int64_pod rather than a HOST_WIDE_INT.
	(get_addr_base_and_unit_offset): Likewise.
	* tree-dfa.c (get_addr_base_and_unit_offset_1): Likewise.
	(get_addr_base_and_unit_offset): Likewise.
	* doc/match-and-simplify.texi: Change off from HOST_WIDE_INT
	to poly_int64 in example.
	* fold-const.c (fold_binary_loc): Update call to
	get_addr_base_and_unit_offset.
	* gimple-fold.c (gimple_fold_builtin_memory_op): Likewise.
	(maybe_canonicalize_mem_ref_addr): Likewise.
	(gimple_fold_stmt_to_constant_1): Likewise.
	* gimple-ssa-warn-restrict.c (builtin_memref::builtin_memref):
	Likewise.
	* ipa-param-manipulation.c (ipa_modify_call_arguments): Likewise.
	* match.pd: Likewise.
	* omp-low.c (lower_omp_target): Likewise.
	* tree-sra.c (build_ref_for_offset): Likewise.
	(build_debug_ref_for_model): Likewise.
	* tree-ssa-address.c (maybe_fold_tmr): Likewise.
	* tree-ssa-alias.c (ao_ref_init_from_ptr_and_size): Likewise.
	* tree-ssa-ccp.c (optimize_memcpy): Likewise.
	* tree-ssa-forwprop.c (forward_propagate_addr_expr_1): Likewise.
	(constant_pointer_difference): Likewise.
	* tree-ssa-loop-niter.c (expand_simple_operations): Likewise.
	* tree-ssa-phiopt.c (jump_function_from_stmt): Likewise.
	* tree-ssa-pre.c (create_component_ref_by_pieces_1): Likewise.
	* tree-ssa-sccvn.c (vn_reference_fold_indirect): Likewise.
	(vn_reference_maybe_forwprop_address, vn_reference_lookup_3): Likewise.
	(set_ssa_val_to): Likewise.
	* tree-ssa-strlen.c (get_addr_stridx, addr_stridxptr)
	(maybe_diag_stxncpy_trunc): Likewise.
	* tree-vrp.c (vrp_prop::check_array_ref): Likewise.
	* tree.c (build_simple_mem_ref_loc): Likewise.
	(array_at_struct_end_p): Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255887

This patch changes the types of the bit offsets and sizes returned
by get_ref_base_and_extent to poly_int64.

There are some callers that can't sensibly operate on polynomial
offsets or handle cases where the offset and size aren't known
exactly.  This includes the IPA devirtualisation code (since
there's no defined way of having vtables at variable offsets)
and some parts of the DWARF code.  The patch therefore adds
a helper function get_ref_base_and_extent_hwi that either returns
exact HOST_WIDE_INT bit positions and sizes or returns a null
base to indicate failure.

2017-12-20  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* tree-dfa.h (get_ref_base_and_extent): Return the base, size and
	max_size as poly_int64_pods rather than HOST_WIDE_INTs.
	(get_ref_base_and_extent_hwi): Declare.
	* tree-dfa.c (get_ref_base_and_extent): Return the base, size and
	max_size as poly_int64_pods rather than HOST_WIDE_INTs.
	(get_ref_base_and_extent_hwi): New function.
	* cfgexpand.c (expand_debug_expr): Update call to
	get_ref_base_and_extent.
	* dwarf2out.c (add_var_loc_to_decl): Likewise.
	* gimple-fold.c (get_base_constructor): Return the offset as a
	poly_int64_pod rather than a HOST_WIDE_INT.
	(fold_const_aggregate_ref_1): Track polynomial sizes and offsets.
	* ipa-polymorphic-call.c
	(ipa_polymorphic_call_context::set_by_invariant)
	(extr_type_from_vtbl_ptr_store): Track polynomial offsets.
	(ipa_polymorphic_call_context::ipa_polymorphic_call_context)
	(check_stmt_for_type_change): Use get_ref_base_and_extent_hwi
	rather than get_ref_base_and_extent.
	(ipa_polymorphic_call_context::get_dynamic_type): Likewise.
	* ipa-prop.c (ipa_load_from_parm_agg, compute_complex_assign_jump_func)
	(get_ancestor_addr_info, determine_locally_known_aggregate_parts):
	Likewise.
	* ipa-param-manipulation.c (ipa_get_adjustment_candidate): Update
	call to get_ref_base_and_extent.
	* tree-sra.c (create_access, get_access_for_expr): Likewise.
	* tree-ssa-alias.c (ao_ref_base, aliasing_component_refs_p)
	(stmt_kills_ref_p): Likewise.
	* tree-ssa-dce.c (mark_aliased_reaching_defs_necessary_1): Likewise.
	* tree-ssa-scopedtables.c (avail_expr_hash, equal_mem_array_ref_p):
	Likewise.
	* tree-ssa-sccvn.c (vn_reference_lookup_3): Likewise.
	Use get_ref_base_and_extent_hwi rather than get_ref_base_and_extent
	when calling native_encode_expr.
	* tree-ssa-structalias.c (get_constraint_for_component_ref): Update
	call to get_ref_base_and_extent.
	(do_structure_copy): Use get_ref_base_and_extent_hwi rather than
	get_ref_base_and_extent.
	* var-tracking.c (track_expr_p): Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255886

This patch changes the type of ipa_parm_adjustment::offset from
HOST_WIDE_INT to poly_int64 and updates uses accordingly.

2017-12-20  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* ipa-param-manipulation.h (ipa_parm_adjustment::offset): Change from
	HOST_WIDE_INT to poly_int64_pod.
	* ipa-param-manipulation.c (ipa_modify_call_arguments): Track
	polynomail parameter offsets.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255885

This patch makes the DWARF code use poly_int64 rather than
HOST_WIDE_INT for CFA offsets.  The main changes are:

- to make reg_save use a DW_CFA_expression representation when
  the offset isn't constant and

- to record the CFA information alongside a def_cfa_expression
  if either offset is polynomial, since it's quite difficult
  to reconstruct the CFA information otherwise.

2017-12-20  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* gengtype.c (main): Handle poly_int64_pod.
	* dwarf2out.h (dw_cfi_oprnd_cfa_loc): New dw_cfi_oprnd_type.
	(dw_cfi_oprnd::dw_cfi_cfa_loc): New field.
	(dw_cfa_location::offset, dw_cfa_location::base_offset): Change
	from HOST_WIDE_INT to poly_int64_pod.
	* dwarf2cfi.c (queued_reg_save::cfa_offset): Likewise.
	(copy_cfa): New function.
	(lookup_cfa_1): Use the cached dw_cfi_cfa_loc, if it exists.
	(cfi_oprnd_equal_p): Handle dw_cfi_oprnd_cfa_loc.
	(cfa_equal_p, dwarf2out_frame_debug_adjust_cfa)
	(dwarf2out_frame_debug_cfa_offset, dwarf2out_frame_debug_expr)
	(initial_return_save): Treat offsets as poly_ints.
	(def_cfa_0): Likewise.  Cache the CFA in dw_cfi_cfa_loc if either
	offset is nonconstant.
	(reg_save): Take the offset as a poly_int64.  Fall back to
	DW_CFA_expression for nonconstant offsets.
	(queue_reg_save): Take the offset as a poly_int64.
	* dwarf2out.c (dw_cfi_oprnd2_desc): Handle DW_CFA_def_cfa_expression.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255884

This patch makes operand_subword and operand_subword_force take
polynomial offsets.  This is a fairly old-school interface and
these days should only be used when splitting multiword operations
into word operations.  It still doesn't hurt to support polynomial
offsets and it helps make callers easier to write.

2017-12-20  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* rtl.h (operand_subword, operand_subword_force): Take the offset
	as a poly_uint64 an unsigned int.
	* emit-rtl.c (operand_subword, operand_subword_force): Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255883

This patch changes SUBREG_BYTE from an int to a poly_int.
Since valid SUBREG_BYTEs must be contained within the mode of the
SUBREG_REG, the required range is the same as for GET_MODE_SIZE,
i.e. unsigned short.  The patch therefore uses poly_uint16(_pod)
for the SUBREG_BYTE.

Using poly_uint16_pod rtx fields requires a new field code ('p').
Since there are no other uses of 'p' besides SUBREG_BYTE, the patch
doesn't add an XPOLY or whatever; all uses should go via SUBREG_BYTE
instead.

The patch doesn't bother implementing 'p' support for legacy
define_peepholes, since none of the remaining ones have subregs
in their patterns.

As it happened, the rtl documentation used SUBREG as an example of a
code with mixed field types, accessed via XEXP (x, 0) and XINT (x, 1).
Since there's no direct replacement for XINT, and since people should
never use it even if there were, the patch changes the example to use
INT_LIST instead.

The patch also changes subreg-related helper functions so that they too
take and return polynomial offsets.  This makes the patch quite big, but
it's mostly mechanical.  The patch generally sticks to existing choices
wrt signedness.

2017-12-20  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* doc/rtl.texi: Update documentation of SUBREG_BYTE.  Document the
	'p' format code.  Use INT_LIST rather than SUBREG as the example of
	a code with an XINT and an XEXP.  Remove the implication that
	accessing an rtx field using XINT is expected to work.
	* rtl.def (SUBREG): Change format from "ei" to "ep".
	* rtl.h (rtunion::rt_subreg): New field.
	(XCSUBREG): New macro.
	(SUBREG_BYTE): Use it.
	(subreg_shape): Change offset from an unsigned int to a poly_uint16.
	Update constructor accordingly.
	(subreg_shape::operator ==): Update accordingly.
	(subreg_shape::unique_id): Return an unsigned HOST_WIDE_INT rather
	than an unsigned int.
	(subreg_lsb, subreg_lowpart_offset, subreg_highpart_offset): Return
	a poly_uint64 rather than an unsigned int.
	(subreg_lsb_1): Likewise.  Take the offset as a poly_uint64 rather
	than an unsigned int.
	(subreg_size_offset_from_lsb, subreg_size_lowpart_offset)
	(subreg_size_highpart_offset): Return a poly_uint64 rather than
	an unsigned int.  Take the sizes as poly_uint64s.
	(subreg_offset_from_lsb): Return a poly_uint64 rather than
	an unsigned int.  Take the shift as a poly_uint64 rather than
	an unsigned int.
	(subreg_regno_offset, subreg_offset_representable_p): Take the offset
	as a poly_uint64 rather than an unsigned int.
	(simplify_subreg_regno): Likewise.
	(byte_lowpart_offset): Return the memory offset as a poly_int64
	rather than an int.
	(subreg_memory_offset): Likewise.  Take the subreg offset as a
	poly_uint64 rather than an unsigned int.
	(simplify_subreg, simplify_gen_subreg, subreg_get_info)
	(gen_rtx_SUBREG, validate_subreg): Take the subreg offset as a
	poly_uint64 rather than an unsigned int.
	* rtl.c (rtx_format): Describe 'p' in comment.
	(copy_rtx, rtx_equal_p_cb, rtx_equal_p): Handle 'p'.
	* emit-rtl.c (validate_subreg, gen_rtx_SUBREG): Take the subreg
	offset as a poly_uint64 rather than an unsigned int.
	(byte_lowpart_offset): Return the memory offset as a poly_int64
	rather than an int.
	(subreg_memory_offset): Likewise.  Take the subreg offset as a
	poly_uint64 rather than an unsigned int.
	(subreg_size_lowpart_offset, subreg_size_highpart_offset): Take the
	mode sizes as poly_uint64s rather than unsigned ints.  Return a
	poly_uint64 rather than an unsigned int.
	(subreg_lowpart_p): Treat subreg offsets as poly_ints.
	(copy_insn_1): Handle 'p'.
	* rtlanal.c (set_noop_p): Treat subregs offsets as poly_uint64s.
	(subreg_lsb_1): Take the subreg offset as a poly_uint64 rather than
	an unsigned int.  Return the shift in the same way.
	(subreg_lsb): Return the shift as a poly_uint64 rather than an
	unsigned int.
	(subreg_size_offset_from_lsb): Take the sizes and shift as
	poly_uint64s rather than unsigned ints.  Return the offset as
	a poly_uint64.
	(subreg_get_info, subreg_regno_offset, subreg_offset_representable_p)
	(simplify_subreg_regno): Take the offset as a poly_uint64 rather than
	an unsigned int.
	* rtlhash.c (add_rtx): Handle 'p'.
	* genemit.c (gen_exp): Likewise.
	* gengenrtl.c (type_from_format, gendef): Likewise.
	* gensupport.c (subst_pattern_match, get_alternatives_number)
	(collect_insn_data, alter_predicate_for_insn, alter_constraints)
	(subst_dup): Likewise.
	* gengtype.c (adjust_field_rtx_def): Likewise.
	* genrecog.c (find_operand, find_matching_operand, validate_pattern)
	(match_pattern_2): Likewise.
	(rtx_test::SUBREG_FIELD): New rtx_test::kind_enum.
	(rtx_test::subreg_field): New function.
	(operator ==, safe_to_hoist_p, transition_parameter_type)
	(print_nonbool_test, print_test): Handle SUBREG_FIELD.
	* genattrtab.c (attr_rtx_1): Say that 'p' is deliberately not handled.
	* genpeep.c (match_rtx): Likewise.
	* print-rtl.c (print_poly_int): Include if GENERATOR_FILE too.
	(rtx_writer::print_rtx_operand): Handle 'p'.
	(print_value): Handle SUBREG.
	* read-rtl.c (apply_int_iterator): Likewise.
	(rtx_reader::read_rtx_operand): Handle 'p'.
	* alias.c (rtx_equal_for_memref_p): Likewise.
	* cselib.c (rtx_equal_for_cselib_1, cselib_hash_rtx): Likewise.
	* caller-save.c (replace_reg_with_saved_mem): Treat subreg offsets
	as poly_ints.
	* calls.c (expand_call): Likewise.
	* combine.c (combine_simplify_rtx, expand_field_assignment): Likewise.
	(make_extraction, gen_lowpart_for_combine): Likewise.
	* loop-invariant.c (hash_invariant_expr_1, invariant_expr_equal_p):
	Likewise.
	* cse.c (remove_invalid_subreg_refs): Take the offset as a poly_uint64
	rather than an unsigned int.  Treat subreg offsets as poly_ints.
	(exp_equiv_p): Handle 'p'.
	(hash_rtx_cb): Likewise.  Treat subreg offsets as poly_ints.
	(equiv_constant, cse_insn): Treat subreg offsets as poly_ints.
	* dse.c (find_shift_sequence): Likewise.
	* dwarf2out.c (rtl_for_decl_location): Likewise.
	* expmed.c (extract_low_bits): Likewise.
	* expr.c (emit_group_store, undefined_operand_subword_p): Likewise.
	(expand_expr_real_2): Likewise.
	* final.c (alter_subreg): Likewise.
	(leaf_renumber_regs_insn): Handle 'p'.
	* function.c (assign_parm_find_stack_rtl, assign_parm_setup_stack):
	Treat subreg offsets as poly_ints.
	* fwprop.c (forward_propagate_and_simplify): Likewise.
	* ifcvt.c (noce_emit_move_insn, noce_emit_cmove): Likewise.
	* ira.c (get_subreg_tracking_sizes): Likewise.
	* ira-conflicts.c (go_through_subreg): Likewise.
	* ira-lives.c (process_single_reg_class_operands): Likewise.
	* jump.c (rtx_renumbered_equal_p): Likewise.  Handle 'p'.
	* lower-subreg.c (simplify_subreg_concatn): Take the subreg offset
	as a poly_uint64 rather than an unsigned int.
	(simplify_gen_subreg_concatn, resolve_simple_move): Treat
	subreg offsets as poly_ints.
	* lra-constraints.c (operands_match_p): Handle 'p'.
	(match_reload, curr_insn_transform): Treat subreg offsets as poly_ints.
	* lra-spills.c (assign_mem_slot): Likewise.
	* postreload.c (move2add_valid_value_p): Likewise.
	* recog.c (general_operand, indirect_operand): Likewise.
	* regcprop.c (copy_value, maybe_mode_change): Likewise.
	(copyprop_hardreg_forward_1): Likewise.
	* reginfo.c (simplifiable_subregs_hasher::hash, simplifiable_subregs)
	(record_subregs_of_mode): Likewise.
	* rtlhooks.c (gen_lowpart_general, gen_lowpart_if_possible): Likewise.
	* reload.c (operands_match_p): Handle 'p'.
	(find_reloads_subreg_address): Treat subreg offsets as poly_ints.
	* reload1.c (alter_reg, choose_reload_regs): Likewise.
	(compute_reload_subreg_offset): Likewise, and return an poly_int64.
	* simplify-rtx.c (simplify_truncation, simplify_binary_operation_1):
	(test_vector_ops_duplicate): Treat subreg offsets as poly_ints.
	(simplify_const_poly_int_tests<N>::run): Likewise.
	(simplify_subreg, simplify_gen_subreg): Take the subreg offset as
	a poly_uint64 rather than an unsigned int.
	* valtrack.c (debug_lowpart_subreg): Likewise.
	* var-tracking.c (var_lowpart): Likewise.
	(loc_cmp): Handle 'p'.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255882

Normmaly the IRA-reload interface tries to track the liveness of
individual bytes of an allocno if the allocno is sometimes written
to as a SUBREG.  This isn't possible for variable-sized allocnos,
but it doesn't matter because targets with variable-sized registers
should use LRA instead.

This patch adds a get_subreg_tracking_sizes function for deciding
whether it is possible to model a partial read or write.  Later
patches make it return false if anything is variable.

2017-12-20  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* ira.c (get_subreg_tracking_sizes): New function.
	(init_live_subregs): Take an integer size rather than a register.
	(build_insn_chain): Use get_subreg_tracking_sizes.  Update calls
	to init_live_subregs.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255881

This patch makes store_field and related routines use poly_ints
for bit positions and sizes.  It keeps the existing choices
between signed and unsigned types (there are a mixture of both).

2017-12-20  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* expr.c (store_constructor_field): Change bitsize from a
	unsigned HOST_WIDE_INT to a poly_uint64 and bitpos from a
	HOST_WIDE_INT to a poly_int64.
	(store_constructor): Change size from a HOST_WIDE_INT to
	a poly_int64.
	(store_field): Likewise bitsize and bitpos.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255880

This patch changes C++ bitregion_start/end values from constants to
poly_ints.  Although it's unlikely that the size needs to be polynomial
in practice, the offset could be with future language extensions.

2017-12-20  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* expmed.h (store_bit_field): Change bitregion_start and
	bitregion_end from unsigned HOST_WIDE_INT to poly_uint64.
	* expmed.c (adjust_bit_field_mem_for_reg, strict_volatile_bitfield_p)
	(store_bit_field_1, store_integral_bit_field, store_bit_field)
	(store_fixed_bit_field, store_split_bit_field): Likewise.
	* expr.c (store_constructor_field, store_field): Likewise.
	(optimize_bitfield_assignment_op): Likewise.  Make the same change
	to bitsize and bitpos.
	* machmode.h (bit_field_mode_iterator): Change m_bitregion_start
	and m_bitregion_end from HOST_WIDE_INT to poly_int64.  Make the
	same change in the constructor arguments.
	(get_best_mode): Change bitregion_start and bitregion_end from
	unsigned HOST_WIDE_INT to poly_uint64.
	* stor-layout.c (bit_field_mode_iterator::bit_field_mode_iterator):
	Change bitregion_start and bitregion_end from HOST_WIDE_INT to
	poly_int64.
	(bit_field_mode_iterator::next_mode): Update for new types
	of m_bitregion_start and m_bitregion_end.
	(get_best_mode): Change bitregion_start and bitregion_end from
	unsigned HOST_WIDE_INT to poly_uint64.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255879

Similar to the previous store_bit_field patch, but for extractions
rather than insertions.  The patch splits out the extraction-as-subreg
handling into a new function (extract_bit_field_as_subreg), both for
ease of writing and because a later patch will add another caller.

The simplify_gen_subreg overload is temporary; it goes away
in a later patch.

2017-12-20  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* rtl.h (simplify_gen_subreg): Add a temporary overload that
	accepts poly_uint64 offsets.
	* expmed.h (extract_bit_field): Take bitsize and bitnum as
	poly_uint64s rather than unsigned HOST_WIDE_INTs.
	* expmed.c (lowpart_bit_field_p): Likewise.
	(extract_bit_field_as_subreg): New function, split out from...
	(extract_bit_field_1): ...here.  Take bitsize and bitnum as
	poly_uint64s rather than unsigned HOST_WIDE_INTs.  For vector
	extractions, check that BITSIZE matches the size of the extracted
	value and that BITNUM is an exact multiple of that size.
	If all else fails, try forcing the value into memory if
	BITNUM is variable, and adjusting the address so that the
	offset is constant.  Split the part that can only handle constant
	bitsize and bitnum out into...
	(extract_integral_bit_field): ...this new function.
	(extract_bit_field): Take bitsize and bitnum as poly_uint64s
	rather than unsigned HOST_WIDE_INTs.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255878

This patch changes the bitnum and bitsize arguments to
store_bit_field from unsigned HOST_WIDE_INTs to poly_uint64s.
The later part of store_bit_field_1 still needs to operate
on constant bit positions and sizes, so the patch splits
it out into a subfunction (store_integral_bit_field).

2017-12-20  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* expmed.h (store_bit_field): Take bitsize and bitnum as
	poly_uint64s rather than unsigned HOST_WIDE_INTs.
	* expmed.c (simple_mem_bitfield_p): Likewise.  Add a parameter
	that returns the byte size.
	(store_bit_field_1): Take bitsize and bitnum as
	poly_uint64s rather than unsigned HOST_WIDE_INTs.  Update call
	to simple_mem_bitfield_p.  Split the part that can only handle
	constant bitsize and bitnum out into...
	(store_integral_bit_field): ...this new function.
	(store_bit_field): Take bitsize and bitnum as poly_uint64s rather
	than unsigned HOST_WIDE_INTs.
	(extract_bit_field_1): Update call to simple_mem_bitfield_p.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255877

This patch makes LRA use poly_int64s rather than HOST_WIDE_INTs
to store a frame offset (including in things like eliminations).

2017-12-20  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* lra-int.h (lra_reg): Change offset from int to poly_int64.
	(lra_insn_recog_data): Change sp_offset from HOST_WIDE_INT
	to poly_int64.
	(lra_eliminate_regs_1, eliminate_regs_in_insn): Change
	update_sp_offset from a HOST_WIDE_INT to a poly_int64.
	(lra_update_reg_val_offset, lra_reg_val_equal_p): Take the
	offset as a poly_int64 rather than an int.
	* lra-assigns.c (find_hard_regno_for_1): Handle poly_int64 offsets.
	(setup_live_pseudos_and_spill_after_risky_transforms): Likewise.
	* lra-constraints.c (equiv_address_substitution): Track offsets
	as poly_int64s.
	(emit_inc): Check poly_int_rtx_p instead of CONST_INT_P.
	(curr_insn_transform): Handle the new form of sp_offset.
	* lra-eliminations.c (lra_elim_table): Change previous_offset
	and offset from HOST_WIDE_INT to poly_int64.
	(print_elim_table, update_reg_eliminate): Update accordingly.
	(self_elim_offsets): Change from HOST_WIDE_INT to poly_int64_pod.
	(get_elimination): Update accordingly.
	(form_sum): Check poly_int_rtx_p instead of CONST_INT_P.
	(lra_eliminate_regs_1, eliminate_regs_in_insn): Change
	update_sp_offset from a HOST_WIDE_INT to a poly_int64.  Handle
	poly_int64 offsets generally.
	(curr_sp_change): Change from HOST_WIDE_INT to poly_int64.
	(mark_not_eliminable, init_elimination): Update accordingly.
	(remove_reg_equal_offset_note): Return a bool and pass the new
	offset back by pointer as a poly_int64.
	* lra-remat.c (change_sp_offset): Take sp_offset as a poly_int64
	rather than a HOST_WIDE_INT.
	(do_remat): Track offsets poly_int64s.
	* lra.c (lra_update_insn_recog_data, setup_sp_offset): Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255876